Patent application number | Description | Published |
20110025820 | PROGRAM-SPECIFIC PRESENCE - A system and method for providing application specific presence information are disclosed here. A system includes one or more processors, a first communication program executable by the one or more processors, and a second communication program executable the one or more processors. When executed, the first and second communication programs respectively provide a first mode and a second mode of user communication. The second communication program causes the one or more processors to provide user presence information to a communication server. The presence information includes a presence status provided by the first communication program and a separate presence status provided by the second communication program. The separate presence status provided by the second communication program is configured to avoid aggregation, by the communication server, with any other presence status. | 02-03-2011 |
20110029595 | NON-BLOCKING COMMUNICATION BETWEEN AN APPLICATION AND A SERVER - A system and method for providing non-blocking communication with a communications server are disclosed herein. A computer system includes one or more processors and a software system executable by the processor. When executed, the software system provides an application thread and additionally provides a server communication thread configured to provide non-blocking communication between the application thread and a communication server. The server communication thread is configured to process commands based on requests for communication server services generated by the application thread. The server communication thread is further configured to communicate with the communication server based on the commands and to block pending a server response. The application thread is configured to execute unimpeded by the communication. | 02-03-2011 |
20110055893 | COMMUNICATION APPLICATION - In at least some embodiments, a computer system includes a processor and a system memory coupled to the processor. The system memory stores a communication application that, when executed, provides first stage operations and second stage operations. The computer system also includes a network interface coupled to the processor. The first stage operations comprise a selective exchange of primary connection information with a communication endpoint via the network interface. The second stage operations comprise initiating a peer-to-peer communication session with the communication endpoint based on the primary connection information. | 03-03-2011 |
20110099227 | COMMUNICATION APPLICATION WITH STEADY-STATE CONFERENCING - In at least some embodiments, a computer system includes a processor and a network interface coupled to the processor. The computer system also includes a system memory coupled to the processor. The system memory stores a communication application having a steady-state conferencing module and a network manager module. The network manager module, when executed, monitors network changes. The steady-state conferencing module, when executed, maintains a steady-state conferencing user interface while network changes detected by the network manager module are handled. | 04-28-2011 |
20140089385 | APPLICATION VIEWS - In one embodiment, first data, indicative of a first selected application to be accessed via a remoting application, is received at a computer system from a first mobile device. Second data, indicative of a second selected application to be accessed via a remoting application, is received at the computer system from a second mobile device. A first view of the first selected application, as executing at the computer system, is displayed at a first display sector of a display device that is part of the computer system. A second view of the second selected application, as executing at the computer system, is displayed at a second display sector of the display device. At least a portion of the first view is sent to the first mobile device for display, and at least a portion of the second view is sent to the second mobile device for display. | 03-27-2014 |
Patent application number | Description | Published |
20080266999 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM PROVIDING SPARE MEMORY LOCATIONS - A semiconductor memory device having a plurality of memory locations is presented. The plurality of memory locations includes a plurality of primary memory locations and a plurality of spare memory locations. The device includes an address decoder configured to receive a memory location address and process the address to select one of the memory locations. The device further includes control logic configured to receive control signals and process the control signals to determine whether the selected one of the memory locations is one of the primary memory locations or one of the spare memory locations, and to provide access to the selected one of the memory locations via data lines. | 10-30-2008 |
20080270675 | DEFECT MANAGEMENT FOR A SEMICONDUCTOR MEMORY SYSTEM - A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations. | 10-30-2008 |
20100275098 | BIT ERROR RATE REDUCTION BUFFER, METHOD AND APPARATUS - A disclosed example bit error rate reduction buffer comprises a data recovery circuit including differential bit pair inputs and differential bit pair outputs, a CRC circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator, and a serializer including differential bit pair inputs and differential bit pair outputs. The differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit, the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer, the differential bit pair inputs of the data recovery circuit to be driven by a first HSS link, the different bit pair outputs of the serializer to drive a second HSS link; and the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit. | 10-28-2010 |
Patent application number | Description | Published |
20080229035 | SYSTEMS AND METHODS FOR IMPLEMENTING A STRIDE VALUE FOR ACCESSING MEMORY - Systems and methods for implementing a stride valise for memory are provided. One embodiment includes a system comprising a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. The plurality of memory storage units can be defined by a memory range of consecutive addresses. The system also comprises a memory test device configured to access a portion of the plurality of memory storage units in a sequence that repeats according to a programmable stride value. | 09-18-2008 |
20100083030 | REPAIRING HIGH-SPEED SERIAL LINKS - A method and system for repairing high speed serial links is provided. The system includes a first electronic components, connected to at least a second electronic component via at least one link. At least one of the first or second electronic components has a link controller. The link controller is configured to repair serial links by detecting a link error and mapping out individual lanes of a link where the link error is detected. The link controller resumes operation, i.e., transmission of data and continues to monitor the lanes for errors. If and when additional link errors occur, the link controller identifies the lanes in which the link error occurs and deactivates those lanes. The deactivated lane(s) can not be used in further transmissions which, in turn, reduces the occurrence of intermittent link errors. | 04-01-2010 |
20100131810 | SYSTEM AND METHOD FOR IMPLEMENTING A STRIDE VALUE FOR MEMORY TESTING - Systems and methods for implementing a stride value for memory are provided. One embodiment relates to a system that includes a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. A memory test device is configured to perform a memory test that accesses a portion of the plurality of memory storage units in a sequence according to a programmable stride value. The memory test device performs the memory test by writing test data to each of the memory storage units in the portion of the plurality of memory storage units and reading the test data from each of the memory storage units in the portion of the plurality of memory storage units. | 05-27-2010 |
20120203961 | HIGH SPEED INTERFACE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) - An interface for a dynamic random access memory (DRAM) includes an interface element coupled to a DRAM chip using a first attachment structure, a first portion of the first attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second portion of the first attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element configured to convert parallel information to serial information and configured to convert serial information to parallel information. | 08-09-2012 |
20120221996 | SYSTEM AND METHOD FOR DISTRIBUTION ANALYSIS OF STACKED-DIE INTEGRATED CIRCUITS - Systems and methods for distribution analysis of a stacked-die integrated circuit (IC) are described. The stacked-die integrated circuit includes a primary die, and clock load information for the primary die of the IC is determined. Additionally, a clock load model may be created using the clock load information for the primary die. Clock load information for a second die that is coupled to the primary die may also be determined. The clock load information for the second die may be incorporated into the clock load model to create an enhanced clock load model of the stacked-die IC, which may then be analyzed as if a single-die IC. | 08-30-2012 |
20130111123 | A MEMORY SYSTEM THAT UTILIZES A WIDE INPUT/OUTPUT (I/O) INTERFACE TO INTERFACE MEMORY STORAGE WITH AN INTERPOSER AND THAT UTILIZES A SERDES INTERFACE TO INTERFACE A MEMORY CONTROLLER WITH AN INTEGRATED CIRCUIT, AND A METHOD | 05-02-2013 |
20140108683 | MEMORY SYSTEM THAT UTILIZES A WIDE INPUT/OUTPUT (I/O) INTERFACE TO INTERFACE MEMORY STORAGE WITH AN INTERPOSER - A memory system is provided in which at least one memory chip and a memory controller chip are mounted in a side-by-side relationship on an interposer. The memory chip is connected to the interposer via a Wide I/O interface to enable the memory chip and the memory controller chip to communicate with each other via the Wide I/O interface. The memory controller chip has an interface for communicating with an interface of an integrated circuit (IC) chip of the memory system. | 04-17-2014 |