Patent application number | Description | Published |
20130111167 | Uncached Static Short Address Translation Table in the Cache Coherent Computer System | 05-02-2013 |
20130262767 | Concurrently Accessed Set Associative Overflow Cache - An apparatus for concurrently accessing a primary cache and an overflow cache, comprising a core logic unit configured to perform a first instruction that accesses the primary cache and the overflow cache in parallel, determine whether the primary cache stores a requested data, determine whether the overflow cache stores the requested data, and access a main memory when the primary cache and the overflow cache do not store the requested data, wherein the overflow cache stores data that overflows from the primary cache. | 10-03-2013 |
20130339620 | Providing Cache Replacement Notice Using a Cache Miss Request - A computing device has an interface and a processor. The interface is configured to receive a cache miss request from a cache memory, and the processor is configured to identify data that is being removed from the cache memory based at least in part on information obtained from the cache miss request. In another embodiment, a computing device has a memory, a first interface, a processor, and a second interface. The processor is configured to generate a cache miss request when it is determined that data identified in a cache request received through the first interface is not stored in the memory, and the second interface is configured to send the cache miss request to a cache memory. The cache miss request optionally includes an indication of the data identified in the cache request and an indication of a portion of the cached data that is being removed from the memory. | 12-19-2013 |
20140032731 | Recursive, All-to-All Network Topologies - An apparatus comprises an interconnection network comprising N | 01-30-2014 |
20140032853 | Method for Peer to Peer Cache Forwarding - A home node for selecting a source node using a cache coherency protocol, comprising a logic unit cluster coupled to a directory, wherein the logic unit cluster is configured to receive a request for data from a requesting cache node, determine a plurality of nodes that hold a copy of the requested data using the directory, select one of the nodes using one or more selection parameters as the source node, and transmit a message to the source node to determine whether the source node stores a copy of the requested data, wherein the source node forwards the requested data to the requesting cache node when the requested data is found within the source node, and wherein some of the nodes are marked as a Shared state corresponding to the cache coherency protocol. | 01-30-2014 |
20140032854 | Coherence Management Using a Coherent Domain Table - A computer program product comprising computer executable instructions stored on a non-transitory medium that when executed by a processor cause the processor to perform the following: assign a first, second, third, and fourth coherence domain address to a cache data, wherein the first and second address provides the boundary for a first coherence domain, and wherein the third and fourth address provides the boundary for a second coherence domain, inform a first resource about the first coherence domain prior to the first resource executing a first task, and inform a second resource about the second coherence domain prior to the second resource executing a second task. | 01-30-2014 |
20140033209 | Handling of Barrier Commands for Computing Systems - A computing system for handling barrier commands includes a memory, an interface, and a processor. The memory is configured to store a pre-barrier spreading range that identifies a target computing system associated with a barrier command. The interface is coupled to the memory and is configured to send a pre-barrier computing probe to the target computing system identified in the pre-barrier spreading range and receive a barrier completion notification messages from the target computing system. The pre-barrier computing probe is configured to instruct the target computing system to monitor a status of a transaction that needs to be executed for the barrier command to be completed. The processor is coupled to the interface and is configured to determine a status of the barrier command based on the received barrier completion notification messages. | 01-30-2014 |
20140036680 | Method to Allocate Packet Buffers in a Packet Transferring System - A method comprising receiving a credit status from a second node comprising a plurality of credits used to manage the plurality of allocations of storage space in a buffer of the second node, wherein each of the plurality of allocations are dedicated to a different packet type, instructing the second node to use the credit dedicated to a second priority packet type for storing a first priority packet type, wherein the first priority is higher than the second priority, and wherein the credit status reflects the credits for the first priority packet type having reached a minimum value, and transmitting the first priority packet to the second node. | 02-06-2014 |
20140036919 | Forward Progress Assurance and Quality of Service Enhancement in a Packet Transferring System - A method comprising detecting at least one Quality of Service (QoS) requirement is met that indicates a very important packet (VIP) is outstanding from a source node in a multi-hop network comprising multiple nodes, sending an initiation message to an adjacent node in response to the detection that may activate a protocol in which a reserved channel is activated, and receiving the VIP via the reserved channel. Also, a method comprising receiving an initiation message from an adjacent node in a multi-hop network that comprises information identifying the VIP comprising a source node, a destination node, a packet type, wherein the initiation message activates a protocol in which a reserved channel is activated, searching for the VIP identified by the initiation message, and forwarding the VIP promptly if present via the reserved channel or forwarding an initiation message to adjacent nodes closer to the source node. | 02-06-2014 |
20140036929 | Phase-Based Packet Prioritization - A network node comprises a receiver configured to receive a first packet, a processor coupled to the receiver and configured to process the first packet, and prioritize the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and a transmitter coupled to the processor and configured to transmit the first packet. An apparatus comprises a processor coupled to the memory and configured to generate instructions for a packet prioritization scheme, wherein the scheme assigns priority to packet transactions based on closeness to completion, and a memory coupled to the processor and configured to store the instructions. A method comprises receiving a first packet, processing the first packet, prioritizing the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and transmitting the first packet. | 02-06-2014 |
20140036930 | Priority Driven Channel Allocation for Packet Transferring - A method comprising advertising to a second node a total allocation of storage space of a buffer, wherein the total allocation is less than the capacity of the buffer, wherein the total allocation is partitioned into a plurality of allocations, wherein each of the plurality of allocations is advertised as being dedicated to a different packet type, and wherein a credit status for each packet type is used to manage the plurality of allocations, receiving a packet of a first packet type from the second node, and storing the packet to the buffer, wherein the space in the buffer occupied by the first packet type exceeds the advertised space for the first packet type due to the packet. | 02-06-2014 |
20140040561 | HANDLING CACHE WRITE-BACK AND CACHE EVICTION FOR CACHE COHERENCE - A method implemented by a computer system comprising a first memory agent and a second memory agent coupled to the first memory agent, wherein the second memory agent has access to a cache comprising a cache line, the method comprising changing a state of the cache line by the second memory agent, and sending a non-snoop message from the second memory agent to the first memory agent via a communication channel assigned to snoop responses, wherein the non-snoop message informs the first memory agent of the state change of the cache line. | 02-06-2014 |
20140052905 | Cache Coherent Handshake Protocol for In-Order and Out-of-Order Networks - Disclosed herein is a processing network element (NE) comprising at least one receiver configured to receive a plurality of memory request messages from a plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, and a plurality of response messages to the memory requests from the plurality of memory nodes, wherein each memory request designates a source node, a destination node, and a memory location, at least one transmitter configured to transmit the memory requests and memory responses to the plurality of memory nodes, and a controller coupled to the receiver and the transmitter and configured to enforce ordering such that memory requests and memory responses designating the same memory location and the same source node/destination node pair are transmitted by the transmitter in the same order received by the receiver. | 02-20-2014 |
20140052916 | Reduced Scalable Cache Directory - A processing network comprising a cache configured to store copies of memory data as a plurality of cache lines, a cache controller configured to receive data requests from a plurality of cache agents, and designate at least one of the cache agents as an owner of a first of the cache lines, and a directory configured to store cache ownership designations of the first cache line, and wherein the directory is encoded to support substantially simultaneous ownership of the first cache line by a plurality but less than all of the cache agents. Also disclosed is a method comprising receiving coherent transactions from a plurality of cache agents, and storing ownership designations of a plurality of cache lines by the cache agents in a directory, wherein the directory is configured to support storage of substantially simultaneous ownership designations for a plurality but less than all of the cache agents. | 02-20-2014 |
20150117223 | Network Topology of Hierarchical Ring with Gray Coding Shortcuts - An interconnection network comprising a plurality of nodes arranged in a ring topology, wherein the nodes comprise a first node and a second node, and wherein the first node is not adjacent to the second node, a plurality of base links coupled to the nodes and configured to interconnect adjacent nodes to provide point-to-point communications between the adjacent nodes, and a first shortcut coupled to the first node and the second node, wherein the first shortcut is configured to provide a point-to-point communication between the first node and the second node, wherein the first node and the second node comprise gray code encoded addresses that are differed by 1-bit at a particular bit position, and wherein the gray code encoded addresses are node addresses of the first node and the second node encoded by a gray code algorithm that provides a 1-bit difference between successive integer values in a binary format. | 04-30-2015 |
20150117224 | Network Topology of Hierarchical Ring with Gray Code and Binary Code - A hierarchical ring network comprising a plurality of nodes coupled in a base ring configuration such that each node is coupled to two adjacent nodes via base links, wherein the nodes are further coupled via a first level binary shortcut ring such that alternating nodes along the base ring act as first level nodes, and wherein each first level node is coupled to two nearest adjacent first level nodes via the first level binary shortcut ring. | 04-30-2015 |
20150117267 | Network Topology of Hierarchical Ring with Recursive Shortcuts - An interconnection system comprising a plurality of nodes, each comprising at least two ports, and a plurality of links configured to interconnect ports among the nodes to form a hierarchical multi-level ring topology, wherein the ring topology comprises a plurality of levels of rings including a base ring and at least two hierarchical shortcut rings, and wherein each node connected to a higher-level shortcut ring is also connected to all lower-level rings including the base ring. | 04-30-2015 |
Patent application number | Description | Published |
20080266995 | METHOD OF SELECTIVELY POWERING MEMORY DEVICE - An approach to selectively powering a memory device is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various methods are provided to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state. | 10-30-2008 |
20080273412 | MEMORY DEVICE WITH SPLIT POWER SWITCH - A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state. | 11-06-2008 |
20080279310 | ENHANCED SIGNALING SENSITIVITY USING MULTIPLE REFERENCES - A receiver circuit uses two or more comparators to detect the received data signal. Each comparator is set to compare the data signal to a different reference signal. The output signals of the comparators are received into a detector circuit, which provides a third output signal that establishes the logic state of the received signal based on whether or not the output signals of the comparators are equal. Depending on the logic state of the data signal, one of the comparators provides its output signal sooner than the other. Each comparator may be implemented by a differential amplifier. In one embodiment, the reference signals are threshold voltages which may be provided by the tripping voltages at the trip points for the logic HIGH and LOW states. | 11-13-2008 |
20080309408 | SYMMETRICAL DIFFERENTIAL AMPLIFIER - A differential amplifier has improved power efficiency, reduced offset penalty and a symmetrical output differential signal. Such a differential amplifier may include: (a) a bias circuit that has a first input device and a second input device; (b) a first load device and a second load device, each biased by a bias voltage from the bias circuit; and (c) a third input device and a fourth input device that are connected in series with the first load device and the second load device, respectively. In that differential amplifier, the differential input signal is applied across the first and second input devices, as well as across the third and the fourth input devices. The first, second, third and fourth input devices are sized such that a total current in the first and second input devices bears a predetermined ratio to a total current in the third and fourth input devices. | 12-18-2008 |