Patent application number | Description | Published |
20080266981 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device. | 10-30-2008 |
20080268592 | Flash memory device and method of fabricating the same - Provided are a flash memory device and a method of fabricating the same. The method includes forming a first dielectric layer on an active region of a semiconductor substrate. A first conductive layer is formed on the semiconductor substrate having the first dielectric layer. A mask pattern is formed on the first conductive layer. Using the mask pattern as an etch mask, the first conductive layer is etched to form a first conductive pattern narrowing from its upper surface toward its middle portion. A second dielectric layer is formed on the semiconductor substrate having the first conductive pattern. A second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern is formed on the semiconductor substrate having the second dielectric layer. | 10-30-2008 |
20080283873 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via. | 11-20-2008 |
20080316831 | Nonvolatile semiconductor device, system including the same, and associated methods - A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the memory cell units includes a tunnel insulation layer on the semiconductor substrate. A first memory gate and a second memory gate are disposed on the tunnel insulation layer. An isolation gate is disposed between the first and second memory gates. A word line covers the first memory gate, the second memory gate and the isolation gate. A method of forming the nonvolatile memory device is also provided. | 12-25-2008 |
20080318406 | SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level. | 12-25-2008 |
20090059664 | Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same - In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated. | 03-05-2009 |
20090121277 | Nonvolatile memory device and method of manufacturing the same - The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer. | 05-14-2009 |
20090141562 | NON-VOLATILE MEMORY DEVICE, METHODS OF FABRICATING AND OPERATING THE SAME - A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data. | 06-04-2009 |
20090189210 | Semiconductor Flash Memory Device and Method of Fabricating the Same - A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess. | 07-30-2009 |
20090278192 | SEMICONDUCTOR DEVICE - A semiconductor device includes a tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate structure. The tunnel insulation layer pattern is formed on a substrate. The charge trapping layer pattern is formed on the tunnel insulation layer pattern. The blocking layer pattern is formed on the substrate and extends up onto and covers the charge trapping layer pattern. The gate surrounds an upper portion of the charge trapping layer pattern so as to face towards and upper surface and opposite side surfaces of the charge trapping layer pattern. | 11-12-2009 |
20090286369 | Method of manufacturing a semiconductor device - In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold. | 11-19-2009 |
20100001328 | SEMICONDUCTOR DEVICE HAVING AN ANTI-PAD PEELING-OFF STRUCTURE - A bonding pad having an anti-pad peeling-off structure is disclosed. In a method of forming the bonding pad, after a metal pad layer is formed, a slit is formed in the metal pad layer. A protecting layer is formed on the metal pad layer. The protecting layer is partially removed to expose the metal pad such that a portion of the protecting layer remains in the slits to be connected to the main protecting layer. The protecting layer formed in the slit is connected to the protecting layer such that the residual protecting layer pattern buffer when physical impacts are generated, to prevent peeling-off of the metal pad layer. | 01-07-2010 |
20100059888 | Mask ROM and method of fabricating the same - A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes. | 03-11-2010 |
20100103744 | Non-volatile memory device and method of driving the same - A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors. | 04-29-2010 |
20100197109 | METHOD OF FORMING ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE - Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed. | 08-05-2010 |
20100289071 | NON-VOLATILE MEMORY DEVICE, METHODS OF FABRICATING AND OPERATING THE SAME - A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data. | 11-18-2010 |
20100304540 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device. | 12-02-2010 |
20110038210 | Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same - In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated. | 02-17-2011 |
20110175153 | Semiconductor Device Having Transistor with Vertical Gate Electrode and Method of Fabricating the Same - A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern. | 07-21-2011 |
20120068249 | Nonvolatile memory device and method of manufacturing the same - The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer. | 03-22-2012 |