Patent application number | Description | Published |
20080266952 | MEMORY ARRAY ARCHITECTURE FOR A MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY ARRAY ARCHITECTURE - A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells. | 10-30-2008 |
20080304326 | METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE - An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage. | 12-11-2008 |
20080310230 | Flash Memory Devices Having Three Dimensional Stack Structures and Methods of Driving Same - Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled. | 12-18-2008 |
20080316818 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING - A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage. | 12-25-2008 |
20080316825 | SEMICONDUCTOR MEMORY DEVICE - An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal. | 12-25-2008 |
20090010073 | Non-Volatile Memory System Including Spare Array and Method of Erasing a Block in the Same - Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This erasing operation is followed by writing updated overhead data (e.g., an erase count) into the spare array and then performing a soft program operation. This soft program operation is performed on at least a first portion of the main array to thereby narrow a threshold voltage distribution of erased memory cells within the first portion of the main array. The soft program operation is then followed by an operation to verify an erased status of at least the first portion of the main array and an operation to communicate that the main and spare arrays of nonvolatile memory cells have been properly erased to a memory controller. | 01-08-2009 |
20090052257 | NONVOLATILE SEMICONDUCTOR MEMORIES FOR PREVENTING READ DISTURBANCE AND READING METHODS THEREOF - A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line. | 02-26-2009 |
20090097326 | NAND FLASH MEMORY DEVICE HAVING DUMMY MEMORY CELLS AND METHODS OF OPERATING SAME - A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith. | 04-16-2009 |
20090135647 | NAND FLASH MEMORY DEVICES HAVING SHIELDING LINES BETWEEN WORDLINES AND SELECTION LINES - A method of programming a flash memory includes applying a shielding voltage to at least one shielding line, which is interposed between a plurality of wordlines and a selection line and operable to reduce capacitance-coupling between the wordline and the selection line during the programming operation, and applying a program voltage to memory cells through one of the wordlines. | 05-28-2009 |
20090207666 | Methods of Restoring Data in Flash Memory Devices and Related Flash Memory Device Memory Systems - Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages. | 08-20-2009 |
20090290421 | FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit. | 11-26-2009 |
20100002523 | Flash Memory Devices that Utilize Age-Based Verify Voltages to Increase Data Reliability and Methods of Operating Same - Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles. | 01-07-2010 |
20100265769 | SEMICONDUCTOR MEMORY DEVICE - An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal. | 10-21-2010 |
20100271873 | 3-LEVEL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell. | 10-28-2010 |
20100271883 | METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE - An erasing method in a nonvolatile memory device is disclosed. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage, and the post-programming of the dummy memory cells comprises: applying a program voltage to a plurality of dummy word lines coupled to the dummy memory cells to post-program the dummy memory cells; and applying a pass voltage to a plurality of normal word lines coupled to the normal memory cells so that the normal memory cells are not post-programmed. | 10-28-2010 |
20110090738 | NAND FLASH MEMORY DEVICE HAVING DUMMY MEMORY CELLS AND METHODS OF OPERATING SAME - A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith. | 04-21-2011 |
20110235432 | METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE - An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage. | 09-29-2011 |