Patent application number | Description | Published |
20100308935 | SWITCHED-CAPACITOR BAND-PASS FILTER OF A DISCRETE-TIME TYPE, IN PARTICULAR FOR CANCELLING OFFSET AND LOW-FREQUENCY NOISE OF SWITCHED-CAPACITOR STAGES - A band-pass filter made up by an operational amplifier and by an input circuit. The input circuit is formed by a capacitive filtering element, connected to the input of the operational amplifier; a coupling switch, coupled between an input node and the capacitive filtering element; a capacitive sampling element, coupled between the input of the filter and the input node; and a sampling switch, coupled between the input node and a reference-potential line. The coupling switch and the input sampling switch close in phase opposition according to a succession of undesired components sampling and sensing steps, so that the capacitive sampling element forms a sampler for sampling the undesired component in the undesired components sampling step, in the absence of the component of interest, and forms a subtractor of the undesired components from the input signal in the sensing step. | 12-09-2010 |
20110140769 | CIRCUIT FOR GENERATING A REFERENCE ELECTRICAL QUANTITY - A circuit for generating a reference electrical quantity, including: a first bipolar transistor and a second bipolar transistor having the base terminals connected to one another and to a common node; a first resistor connected to the emitter terminal of the second bipolar transistor; a first mirror circuit and a second mirror circuit connected to the first and second bipolar transistors, which receive, respectively, a first current and a second current and generate, respectively, a first mirrored current and a second mirrored current; a first output stage, which generates the reference electrical quantity as a function of the first and second mirrored currents; and a second resistor connected to the common node. The first current is a function of the current in the first resistor, whilst the second current is a function of the current in the second resistor. | 06-16-2011 |
20110148468 | THRESHOLD COMPARATOR WITH HYSTERESIS AND METHOD FOR PERFORMING THRESHOLD COMPARISON WITH HYSTERESIS - A threshold comparator with hysteresis includes a comparator circuit, having a first input, for receiving an input voltage, a second input, and an output, which supplies an output voltage having a first value and a second value. A current generator, controlled by the output voltage, supplies a current to the first input in the presence selectively of one between the first value and second value of the output voltage. A selector circuit connects the second input of the comparator circuit to a first reference voltage source, which supplies a first reference voltage, in response to first edges of the output voltage, and to a second reference voltage source, which supplies a second reference voltage, in response to second edges of the output voltage, opposite to the first edges. | 06-23-2011 |
20130025368 | MICROELECTROMECHANICAL GYROSCOPE WITH IMPROVED READING STAGE AND METHOD - A gyroscope, including: a body; a driving mass, mobile along a driving axis; a driving device that keeps the driving mass in oscillation according to the driving axis at a driving frequency; a sensing mass, coupled to the driving mass to move according to the driving axis and is mobile with respect to the driving mass along a sensing axis; and a reading device, which receives a sensing signal associated with the movement of the sensing mass and supplies an output signal indicating a position of the sensing mass. The reading device includes an analog-to-digital converter, which receives a voltage signal associated with the sensing signal. The voltage signal includes a useful signal component and a spurious signal component, phase-shifted with respect to one another by approximately 90°, and the analog-to-digital converter is configured for sampling the voltage signal at maximum values assumed by the useful signal component. | 01-31-2013 |
20130033274 | MICROELECTROMECHANICAL SENSOR WITH DIFFERENTIATED PERFORMANCES AND METHOD OF CONTROLLING A MICROELECTROMECHANICAL SENSOR - A microelectromechanical sensor includes a supporting structure and a sensing mass, which is elastically coupled to the supporting structure, is movable with respect thereto with one degree of freedom in response to movements according to an axis and is coupled to the supporting structure through a capacitive coupling. A sensing device senses, on terminals of the capacitive coupling, transduction signals indicative of displacements of the first sensing mass according to the degree of freedom. The sensing device includes at least one first reading chain, having first operative parameters, one second reading chain, having second operative parameters different from the first operative parameters, and one selective electrical connection structure that couples the first reading chain and the second reading chain to the first terminals. | 02-07-2013 |
20130285767 | SWITCHED-CAPACITOR BAND-PASS FILTER OF A DISCRETE-TIME TYPE, IN PARTICULAR FOR CANCELLING OFFSET AND LOW-FREQUENCY NOISE OF SWITCHED-CAPACITOR STAGES - A band-pass filter made up by an operational amplifier and by an input circuit. The input circuit is formed by a capacitive filtering element, connected to the input of the operational amplifier; a coupling switch, coupled between an input node and the capacitive filtering element; a capacitive sampling element, coupled between the input of the filter and the input node; and a sampling switch, coupled between the input node and a reference-potential line. The coupling switch and the input sampling switch close in phase opposition according to a succession of undesired components sampling and sensing steps, so that the capacitive sampling element forms a sampler for sampling the undesired component in the undesired components sampling step, in the absence of the component of interest, and forms a subtractor of the undesired components from the input signal in the sensing step. | 10-31-2013 |
Patent application number | Description | Published |
20090044061 | STRUCTURE AND METHOD FOR DETECTING ERRORS IN A MULTILEVEL MEMORY DEVICE WITH IMPROVED PROGRAMMING GRANULARITY - An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block. | 02-12-2009 |
20100140488 | Increasing the Spatial Resolution of Dosimetry Sensors - A two-dimensional array of memory cells may be used to implement a spatial dosimeter. The two-dimensional array of cells may be implemented by an integrated circuit memory Because of the relatively small size of the integrated circuit memory, the resolution of the resulting array may be less than 100 nanometers. The change in threshold voltage of each of the cells, as a result of radiation exposure, may be used to calculate the dose seen at each cell, allowing dose profiles in two dimensions with sub-micrometer resolution. | 06-10-2010 |
20110249501 | DYNAMIC POLARIZATION FOR REDUCING STRESS INDUCED LEAKAGE CURRENT - Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current. | 10-13-2011 |
20120106260 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells. | 05-03-2012 |
20120224430 | READING MEMORY CELL HISTORY DURING PROGRAM OPERATION FOR ADAPTIVE PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device. | 09-06-2012 |
20120279952 | Thermal Treatment of Flash Memories - A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating. | 11-08-2012 |
20130033936 | METHODS TO OPERATE A MEMORY CELL - Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels. | 02-07-2013 |
20130033937 | METHODS FOR PROGRAM VERIFYING A MEMORY CELL AND MEMORY DEVICES CONFIGURED TO PERFORM THE SAME - A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the threshold voltage is located determines the subsequent bit line voltage. The subsequent bit line voltage may be less than a previous bit line voltage used to program the memory cell. | 02-07-2013 |
20130258774 | READING MEMORY CELL HISTORY DURING PROGRAM OPERATION FOR ADVAPTIVE PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device. | 10-03-2013 |
20140321206 | READING MEMORY CELL HISTORY DURING PROGRAM OPERATION FOR ADAPTIVE PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device. | 10-30-2014 |
Patent application number | Description | Published |
20080266929 | REFERENCE CELL LAYOUT WITH ENHANCED RTN IMMUNITY - A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells. | 10-30-2008 |
20100214839 | NAND FLASH MEMORY STRING APPARATUS AND METHODS OF OPERATION THEREOF - A NAND string, its operation, and manufacture is described herein. The NAND string includes one or more memory cells, a first selection transistor coupled to the memory cells, and a second selection transistor coupled between the memory cell and the first selection transistor, wherein the second selection transistor has a process defined threshold voltage. | 08-26-2010 |
20140185387 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells. | 07-03-2014 |
20140245107 | REARRANGING WRITE DATA TO AVOID HARD ERRORS - This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error. | 08-28-2014 |
20150114946 | THERMAL TREATMENT OF FLASH MEMORIES - A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating. | 04-30-2015 |
20150149838 | REARRANGING PROGRAMMING DATA TO AVOID HARD ERRORS - This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error. | 05-28-2015 |
Patent application number | Description | Published |
20130041644 | AUTOMATED UPGRADING METHOD FOR CAPACITY OF IT SYSTEM RESOURCES - Embodiments provide a method for performing an automatic execution of a Box and Jenkins method for forecasting the behavior of said dataset. The method may include pre-processing the dataset including providing one or more missing values to the dataset, removing level discontinuities and outliers, and removing one or more last samples from the dataset, obtaining a trend of the pre-processed dataset including identifying and filtering the trend out of the dataset based on a coefficient of determination methodology, detecting seasonality to obtain a resulting stationary series including computing an auto correlation function of the dataset, repeating the detecting step on an aggregate series of a previous dataset, and removing detected seasonality based on a seasonal differencing process, and modeling the resulting stationary series under an autoregressive-moving-average (ARMA) model. | 02-14-2013 |
20130103826 | AUTOMATED SERVICE TIME ESTIMATION METHOD FOR IT SYSTEM RESOURCES - Embodiments provide a method for upgrading resources in a system including normalizing a collected dataset, scattering data from the normalized dataset, obtaining a plurality of clusters based on the scattered data, discarding one or more clusters from the plurality of clusters with less than a percentage of a total number of observations, in each cluster, performing clusterwise regression and obtaining linear sub-clusters in a defined number, reducing one or more sub-clusters including applying a refinement procedure, removing one or more sub-clusters that fit to outliers and merging pairs of clusters that fit an equivalent model, updating one or more clusters with the reduced sub-clusters, removing one or more globular clusters, reducing a number of clusters with the refinement procedure, and de-normalizing one or more results. | 04-25-2013 |
20140095693 | Automated Capacity Aware Provisioning - According to one general aspect, a method may include monitoring, via a communications network, an actual system resource usage of each of a plurality of target computing devices configured to execute one or more respective workload tasks. The method may also include receiving a request for a suggestion for an assigned target computing device to be assigned a new workload task. The method may further include providing the suggestion regarding the assigned target computing device to be assigned a new workload task, wherein the suggestion suggests one or more target computing device(s) that is included in the plurality of target computing devices. The method may also include adjusting a system resource usage profile of the assigned target computing device to include an estimated system resource usage for the new workload task and an actual system resource usage of the assigned target computing device that was previously monitored. | 04-03-2014 |