Patent application number | Description | Published |
20110317547 | METHOD AND DEVICE FOR THE RELIABLE TRANSMISSION OF DATA PACKET FLOWS WITH COMPRESSED HEADERS WITHOUT INCREASING THE FLOW RATE - A method for robustly transmitting a data flow in the form of packets Pi including at least one header Hi, said header being compressed via a first header compression step, said packets being fragmented into a succession of cells, said cells having an identical fixed size, said fragmentation resulting in the appearance of a padding section in the last of said cells, where the space occupied by said padding section is used, at least partially, to insert redundancy data, the function of said redundancy data being to increase the robustness to transmission errors of said compressed header. | 12-29-2011 |
20120154532 | TRANSMISSION METHOD AND SYSTEM USING AN ADAPTIVE AND PROGRAMMABLE HIERARCHICAL MODULATION - A method for transmission of a signal simultaneously including a first stream of binary data and one or more other streams of binary data, the method including, in the following order: dynamic distribution of bits of the data streams between coders, with one coder per data stream; coding the distributed bits using the coders; dynamic distribution of the coded bits between hierarchical levels of a modulator; and hierarchical modulation using the modulator. | 06-21-2012 |
20140355516 | METHODS FOR TRANSMITTING AND RECEIVING DATA BETWEEN A TERMINAL AND A GATEWAY, IN PARTICULAR VIA A SATELLITE LINK - A method for transmitting data between a terminal and a gateway, the data being transported by Ethernet frames comprising an Ethernet header and a payload, which are themselves encapsulated in lower level packets each comprising a header containing a medium access address, comprises the following steps: determining contexts common to frames whose Ethernet headers have identical fields, and defining an identifier of each the context; associating all or some of the frames with the corresponding context identifiers and suppressing the fields from their Ethernet headers; and introducing the context identifier of each frame for which the fields of the Ethernet header have been suppressed from the header of the lower level packet encapsulating it by replacing its medium access address. A method for receiving data transmitted by means of such a method. | 12-04-2014 |
Patent application number | Description | Published |
20080266787 | On-Chip Interconnect-Stack Cooling Using Sacrificial Interconnect Segments - The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fluidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of electrical interconnect segments and at desired lateral positions of fluidic-cooling channel segments. A metal filling is deposited in the recesses of the dielectric layer sequence so as to form the electrical interconnect segments and to form a sacrificial filling in the fluidic-cooling channel segments. Afterwards, the sacrificial metal filling is selectively removed from the fluidic-cooling channel segments. | 10-30-2008 |
20090051033 | RELIABILITY IMPROVEMENT OF METAL-INTERCONNECT STRUCTURE BY CAPPING SPACERS - The present invention relates to a metal-interconnect structure for electrically connecting integrated-circuit elements in an integrated-circuit device. It solves several problems of operational reliability in damascene interconnect structures, due to corner effects and structural defects present at top edges of interconnect lines fabricated according to prior-art processing technologies. In alternative configurations of the metal interconnect structure, capping spacers ( | 02-26-2009 |
20090218699 | METAL INTERCONNECTS IN A DIELECTRIC MATERIAL - A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material. | 09-03-2009 |
20100044865 | FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS - A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved. | 02-25-2010 |
20100120243 | FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS - The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element. | 05-13-2010 |
20100323477 | INTERCONNECTIONS OF AN INTEGRATED ELECTRONIC CIRCUIT - A method to fabricate an integrated electronic circuit includes superimposing insulating layers and metal elements distributed within said insulating layers. Each insulating layer comprises a first level within which the metal elements lie substantially in the plane of the first level, and a second level traversed by the metal elements in a direction substantially perpendicular to the plane of the second level, so as to come into contact with at least one metal element of the first level. The levels also comprise insulation zones for insulating the metal elements from each other. In one insulating layer, at least one of the levels comprises at least two insulation zones respectively realized of a first material and a second material which are different from each other. | 12-23-2010 |