Patent application number | Description | Published |
20090015414 | METHOD AND APPARATUS FOR SECURE TRANSACTIONS IN A RFID INVENTORY FLOW UTILIZING ELECTRICALLY PROGRAMMABLE FUSES - A security tag adapted for use with a radiofrequency identification (RFID) system, includes: circuitry for at least one of transmitting and receiving an RFID signal, at least one one-time-programmable-read-only-memory (OTPROM) and at least one fuse (eFUSE) coupled to the OTPROM; wherein the circuitry is adapted for communication with the OTPROM and providing instructions for at least one of selectively reading the at least one fuse and selectively blowing the at least one fuse. | 01-15-2009 |
20120126330 | Enhanced Thin Film Field Effect Transistor Integration into Back End of Line - A semiconductor chip has self aligned (where a gate electrode and associated spacers define the source/drain implant with respect to the gate electrode) Field Effect Transistors (FETs) in a back end of the line (BEOL) portion of the semiconductor chip. The FETs are used to make buffer circuits in the BEOL to improve delay and signal integrity of long signal paths on the semiconductor chip. | 05-24-2012 |
20120175624 | IMPLEMENTING VERTICAL SIGNAL REPEATER TRANSISTORS UTILIZING WIRE VIAS AS GATE NODES - A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor. | 07-12-2012 |
20120175626 | IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS - A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node. | 07-12-2012 |
20120216301 | IMPLEMENTING HACKING DETECTION AND BLOCK FUNCTION AT INDETERMINATE TIMES WITH PRIORITIES AND LIMITS - A method and circuits for implementing a hacking detection and block function at indeterminate times, and a design structure on which the subject circuit resides are provided. A circuit includes an antenna wrapped around a dynamic bus inside circuitry to be protected. The antenna together with the dynamic bus node is designed so an average bus access activates a field effect transistor (FET) that is connected to a capacitor. The FET drains the capacitor in a specified number of activations by the antenna. The capacitor has a leakage path to a voltage supply rail VDD that charges the capacitor back high after a time, such as ten to one hundred cycles, of the dynamic bus being quiet. The capacitor provides a hacking detect signal for temporarily blocking operation of the circuitry to be protected responsive to determining that the dynamic bus is more active than functionally expected. | 08-23-2012 |
20120267697 | eDRAM HAVING DYNAMIC RETENTION AND PERFORMANCE TRADEOFF - A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM deep trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. Retention time and performance of the eDRAM is controlled by applying a voltage to the independently voltage controlled silicon region. | 10-25-2012 |
20120267752 | INDEPENDENTLY VOLTAGE CONTROLLED VOLUME OF SILICON ON A SILICON ON INSULATOR CHIP - A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide. | 10-25-2012 |
20120268160 | IMPLEMENTING TEMPORARY DISABLE FUNCTION OF PROTECTED CIRCUITRY BY MODULATING THRESHOLD VOLTAGE OF TIMING SENSITIVE CIRCUIT - A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail. | 10-25-2012 |
20120268195 | IMPLEMENTING eFUSE CIRCUIT WITH ENHANCED eFUSE BLOW OPERATION - A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function. | 10-25-2012 |
20130043544 | STRUCTURE HAVING THREE INDEPENDENT FINFET TRANSISTORS - A semiconductor chip has a FinFET structure with three independently controllable FETs on a single fin. The three FETs are connected in parallel so that current will flow between a common source and a common drain if one or more of the three independently controllable FETs is turned on. The three independently controllable FETs may be used in logic gates. | 02-21-2013 |
20130082268 | IMPLEMENTING VERTICAL SIGNAL REPEATER TRANSISTORS UTILIZING WIRE VIAS AS GATE NODES - A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor. | 04-04-2013 |
20130126881 | IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS - A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node. | 05-23-2013 |
20130146992 | DEEP TRENCH EMBEDDED GATE TRANSISTOR - A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the source to the drain. | 06-13-2013 |
20130263075 | UTILIZING GATE PHASES FOR CIRCUIT TUNING - Implementing circuit tuning post design of an integrated circuit utilizing gate phases. Each phase includes a designation of one of a slow phase and a fast phase. During the circuit design phase, each device is given a phase designation based upon expected performance of the device in the circuit. If the device is expected to be in a critical path or has a minimum timing slack, the device is placed on the fast phase. If the device is not in a critical path or has excess timing slack the device is placed on the slow phase. | 10-03-2013 |
20130313441 | Soft Error Detection - An apparatus includes a first radiation detector to generate a first signal when a first radiation level is exceeded and a second radiation detector to generate a second signal when a second radiation level is exceeded. The second radiation level is greater than the first radiation level. A first circuit is susceptible to soft errors at the first radiation level and a second circuit is susceptible to soft errors at the second radiation level. A control unit may suspend use of the first circuit and activate use of the second circuit if the first signal is received and the second signal is not received. The first and second circuits may be memory cells or logic circuits. | 11-28-2013 |
20130328159 | IMPLEMENTING ISOLATED SILICON REGIONS IN SILICON-ON-INSULATOR (SOI) WAFERS USING BONDED-WAFER TECHNIQUE - Methods and structures are provided for implementing independently voltage controlled isolated silicon regions under a buried oxide layer for biasing field effect transistors above the buried oxide layer on Silicon-on-Insulator (SOI) wafers. Using a bonded-wafer technique, a first bulk substrate wafer is bonded with a second wafer providing a buried oxide (BOX) layer under a transistor silicon layer creating an SOI wafer. An independently voltage controlled isolated silicon region is created in the created SOI wafer beneath the BOX layer. The transistor silicon layer is polished to a desired thickness, and normal processing is continued with transistors and desired circuits placed over the isolated silicon region. A contact is formed through the transistor silicon layer and BOX layer to the isolated silicon region for connecting the independently voltage controlled isolated silicon region to a voltage. | 12-12-2013 |
20130341720 | IMPLEMENTING GATE WITHIN A GATE UTILIZING REPLACEMENT METAL GATE PROCESS - A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage. | 12-26-2013 |
20130341724 | FinFET with Body Contact - A semiconductor device has a FinFET with at least two independently controllable FETs on a single fin. The fin may have a body area with a width between two vertical sides, each side has a single FET. The fin also may have a top fin area that is wider than the body area and is electrically independent from the two FETs. The top fin area may be capable of receiving a body contact structure which may be connected to an electrical conductor as to regulate the voltage in the body area of the fin. | 12-26-2013 |
20130341733 | Plural Differential Pair Employing FinFET Structure - A plural differential pair may include a first semiconductor fin having first and second drain areas. First and second body areas may be disposed on the fin between the first and second drain areas. A source area may be disposed on the fin between the first and second body areas. The plural differential pair may include a first pair of fin field effect (FinFET) transistors and a second pair of FinFET transistors. The plural differential pair may include first and second top fin areas projecting from respective portions of a top side of the first and second body areas of the fin. The first and second top fin areas may each have a width that is wider than the first and second body areas of the fin. | 12-26-2013 |
20140151896 | IMPLEMENTING ENHANCED POWER SUPPLY DISTRIBUTION AND DECOUPLING UTILIZING TSV EXCLUSION ZONE - Methods and structures implement enhanced power supply distribution and decoupling utilizing Through-Silicon-Via (TSV) exclusion zone areas for contacting one or more metal wiring layers on a semiconductor chip. A first wiring level in the TSV exclusion zone area includes a first wiring shape having a first hole of a first diameter. A dielectric includes second hole of a second diameter larger than the first diameter is provided above the first wiring level concentric with the first hole. A via hole extends through the first and second holes and an etch is performed to expose a top surface portion of the first wiring shape. A thin oxide is grown over the entire bore of the hole; an anisotropic etch is provided to remove horizontal portions of the thin oxide, exposing wiring shapes. The via hole is filled with a selected material to make TSV electrical connection to the exposed wiring shape. | 06-05-2014 |
20140183640 | GATELESS FINFET - A finFET includes a semiconductor fin formed on a base. The fin further includes a body area between a first vertical surface and a second vertical surface. The finFET includes a first contact adjacent to the first vertical surface of the body area. The first vertical surface is spaced away from the first contact by a first dielectric thickness. Also included is a second contact adjacent to the second vertical surface of the body area. The second vertical surface is spaced away from the second contact by a second dielectric thickness. The first dielectric thickness and second dielectric thickness are configured to allow the first contact and second contact to modulate the body area of the fin. | 07-03-2014 |
20140253220 | ELECTRONIC FUSE CELL AND ARRAY - Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node. | 09-11-2014 |
20140264332 | SEMICONDUCTOR CHIP WITH POWER GATING THROUGH SILICON VIAS - A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground. | 09-18-2014 |
20140362635 | CAPACITOR BACKUP FOR SRAM - Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node. | 12-11-2014 |
20140362636 | CAPACITOR BACKUP FOR SRAM - Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node. | 12-11-2014 |
20150076615 | INTERDIGITATED FINFETS - A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer. | 03-19-2015 |
Patent application number | Description | Published |
20080266735 | Method and Apparatus for Implementing APS Voltage Level Activation With Secondary Chip in Stacked-Chip Technology - A method and apparatus implement adaptive power supply (APS) system voltage level activation eliminating the use of electronic Fuses (eFuses). A primary chip includes an adaptive power supply (APS). A secondary chip circuit includes at least one pair of hard-wired APS setting connections. Each hard-wired APS setting connection is defined by a selected one of a voltage supply connection and a ground potential connection. A respective inverter couples a control signal from each of the hard-wired APS setting connections to a power communication bus connected to the APS on the primary chip. | 10-30-2008 |
20080266736 | Method and Apparatus for Implementing APS Voltage Level Activation With Secondary Chip in Stacked-Chip Technology - A method and apparatus implement adaptive power supply (APS) system voltage level activation eliminating the use of electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. A primary chip includes an adaptive power supply (APS). A secondary chip circuit includes at least one pair of hard-wired APS setting connections. Each hard-wired APS setting connection is defined by a selected one of a voltage supply connection and a ground potential connection. A respective inverter couples a control signal from each of the hard-wired APS setting connections to a power communication bus connected to the APS on the primary chip. | 10-30-2008 |
20090175106 | APPARATUS FOR IMPLEMENTING EFUSE SENSE AMPLIFIER TESTING WITHOUT BLOWING THE EFUSE - Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem. | 07-09-2009 |
20090201074 | Method and Circuit for Implementing Efuse Sense Amplifier Verification - A method and circuit for implementing Efuse sense amplifier verification, and a design structure on which the subject circuit resides are provided. A first predefined resistor value is sensed relative to a reference resistor. A second predefined resistor value is sensed relative to a reference resistor. Responsive to identifying a respective sense amplifier output resulting from the sensing steps of an unblown eFuse and a blown eFuse, valid operation of the sense amplifier is identified. | 08-13-2009 |
20090201756 | Method and Circuit for Implementing Enhanced Efuse Sense Circuit - A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline. | 08-13-2009 |
20090212850 | Method and Circuit for Implementing Efuse Resistance Screening - A method and circuit for implementing eFuse resistance screening, and a design structure on which the subject circuit resides are provided. An eFuse is sensed using a first reference resistor. Responsive to the eFuse being sensed as blown with the first reference resistor, the eFuse is sensed using a second reference resistor having a higher resistance than the first reference resistor. Responsive to the eFuse being sensed as unblown with the second reference resistor, the eFuse is recorded as poorly blown. Reliability concerns are identified quickly and accurately without being required to measure the resistance of the eFuse. | 08-27-2009 |
20100067319 | Implementing Precise Resistance Measurement for 2D Array Efuse Bit Cell Using Differential Sense Amplifier, Balanced Bitlines, and Programmable Reference Resistor - A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected to the balanced odd and even bitlines. First a baseline current measurement is made through one of the programmable reference resistors, and used to identify a network baseline resistance. A current measurement is made for an eFuse path including a selected eFuse and used to identify the resistance of the selected eFuse. | 03-18-2010 |