Patent application number | Description | Published |
20080263530 | METHOD AND SYSTEM FOR AUTOMATED CODE CONVERSION - A method and system for converting application code into optimized application code or into execution code suitable for execution on a computation engine with an architecture comprising at least a first and a second level of data memory units are disclosed. In one aspect, the method comprises obtaining application code, the application code comprising data transfer operations between the levels of memory units. The method further comprises converting at least a part of the application code. The converting of application code comprises scheduling of data transfer operations from a first level of memory units to a second level of memory units such that accesses of data accessed multiple times are brought closer together in time than in the original code. The converting of application code further comprises, after the scheduling of the data transfer operations, deciding on layout of the data in the second level of memory units to improve the data layout locality such that data which is accessed closer together in time is also brought closer together in the layout than in the original code. | 10-23-2008 |
20110055836 | METHOD AND DEVICE FOR REDUCING POWER CONSUMPTION IN APPLICATION SPECIFIC INSTRUCTION SET PROCESSORS - A method and device for converting first program code into second program code, such that the second program code has an improved execution on a targeted programmable platform, is disclosed. In one aspect, the method includes grouping operations on data for joint execution on a functional unit of the targeted platform, scheduling operations on data in time, and assigning operations to an appropriate functional unit of the targeted platform. Detailed word length information, rather than the typically used approximations like powers of two, may be used in at least one of the grouping, scheduling or assigning operations. | 03-03-2011 |
20110230172 | METHOD FOR OPERATING A COMBINED MULTIMEDIA-TELECOM SYSTEM - Presented is a method of managing the operation of a system including a processing subsystem configured to run a multimedia application and a telecommunication subsystem. The method includes determining telecom environment conditions, and selecting a working point from a plurality of predetermined working points. The selecting is based at least in part on the determined environmental conditions. The method also includes setting control parameters in the multimedia application and/or the telecommunication subsystem to configure the system to operate at the selected working point, and operating the system at the selected working point. | 09-22-2011 |
20110305099 | HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM - A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line. | 12-15-2011 |
20120063211 | METHOD FOR IMPROVING WRITABILITY OF SRAM MEMORY - A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell. | 03-15-2012 |
20120063252 | VARIABILITY RESILIENT SENSE AMPLIFIER WITH REDUCED ENERGY CONSUMPTION - An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors. | 03-15-2012 |
20120269060 | METHOD FOR OPERATING A MULTI-MEDIA WIRELESS SYSTEM IN A MULTI-USER ENVIRONMENT - In one aspect, a method of operating a wireless system is disclosed. The method comprises allocating each video packet to a plurality of user specific priority queues. The method further comprises assigning each of the queues to a video quality layer. The method further comprises selectively dropping of one or more of video packets in cases of network congestion based on the video quality layer information. | 10-25-2012 |
20130166616 | System and Method for Implementing a Multiplication - The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction. | 06-27-2013 |
20130198594 | Methods for Viterbi Decoder Implementation - Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget. | 08-01-2013 |
20130222073 | Design and Control of Multi-Temperature Micro-Oven for MEMS Devices - Disclosed are microelectromechanical system (MEMS) devices and methods of using the same. In some embodiments, a MEMS device comprises a micro-oven comprising a MEMS oscillator configured to generate a reference signal. The device further comprises a control unit comprising at least one input node configured to receive a parameter set, where the parameter set comprises at least a first parameter indicative of a sensed ambient temperature, and where the control system is configured to (i) based on the parameter set, select from a plurality of pre-characterized operation temperatures an operation temperature for the MEMS oscillator, and (ii) generate a temperature-setting signal indicating the selected operation temperature. The device still further comprises a temperature control system communicatively coupled to the control unit and configured to (i) receive the temperature-setting signal and (ii) maintain the MEMS oscillator at the selected operation temperature. | 08-29-2013 |
20140019739 | Method for System Scenario Based Design of Dynamic Embedded Systems - Methods are disclosed for system scenario-based design for an embedded platform whereon a dynamic application is implemented. The application meets at least one guaranteed constraint. Temporal correlations are assumed in the behaviour of internal data variables used in the application, with the internal data variables representing parameters used for executing a portion of the application. An example method includes determining a distribution over time of an N-dimensional cost function, with N an integer number N≧1, corresponding to the implementation on the platform for a set of combinations of the internal data variables. The method also includes partitioning an N-dimensional cost space in at least two bounded regions, each bounded region containing cost combinations corresponding to combinations of values of the internal data variables of the set that have similar cost and frequency of occurrence, whereby one bounded region is provided for rarely occurring cost combinations. | 01-16-2014 |
20140071737 | LOCAL WRITE AND READ ASSIST CIRCUITRY FOR MEMORY DEVICE - A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines. | 03-13-2014 |
20140289457 | METHOD AND DEVICE TO REDUCE LEAKAGE AND DYNAMIC ENERGY CONSUMPTION IN HIGH-SPEED MEMORIES - A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit. | 09-25-2014 |
20140312700 | Reconfigurable PV Configuration - A PV module is described with an array of PV cells whereby the module is reconfigurable, allowing different configurations to be applied after installation and during operation, i.e. at run-time. The run time configuration of the module has controllable devices. The main controllable devices are any of (individually or in combination): a) switches which determine the parallel/series connections of the cells as well as hybrid cases also. b) switches between the cells and local dc/dc converters and/or among the DC/DC converters; c) actively controlled bypass diodes placed in order to allow excess current to flow in the occurrence of a mismatch. | 10-23-2014 |