Patent application number | Description | Published |
20080263314 | ADDRESS TRANSLATION APPARATUS WHICH IS CAPABLE OF EASILY PERFORMING ADDRESS TRANSLATION AND PROCESSOR SYSTEM - An address translation apparatus includes first to third retention units, a comparison unit, and a translation unit. The first retention unit retains a multi-bit first address. The second retention unit retains a multi-bit second address different from the first address. The third retention unit retains first information indicating which bit is a translation target in the multi bits of the first address. The comparison unit compares a multi-bit third address input from outside and the first address. The translation unit translates the bit indicated by the first information in the multi bits of the third address to obtain a fourth address such that the bit indicated by the first information coincides with the second address, when the third address coincides with the first address based on comparison result of the comparison unit. | 10-23-2008 |
20090319878 | CHECK CODE GENERATING APPARATUS, METHOD OF GENERATING CHECK CODE, AND COMMUNICATION APPARATUS - A check code generating apparatus generates a first check code that is a check code concerning exclusive OR of first data and second data obtained by rewriting a part of the first data and calculates exclusive OR of the first check code and a second check code that is a check code attached to the first data. | 12-24-2009 |
20100223529 | COMMUNICATION METHOD AND SYSTEM USING TWO OR MORE CODING SCHEMES - A communication method includes causing a transmitter to apply error correcting or detecting code systems to multiple frames or packets and to transmit the multiple frames or packets in succession, causing a receiver to receive the transmitted frames or packets and to decode each of the frames or packets received, and causing the receiver to send an acknowledgment signal to the transmitter on the basis of the results of decoding of the frames or packets. The transmitter applies two or more error correcting or detecting code systems to the frames or packets. | 09-02-2010 |
20150039808 | MEMORY SYSTEM - According to one embodiment, a memory system includes nonvolatile memories each storing data and an address table for acquiring an address of the data, and a control unit which is configured to be capable of accessing the nonvolatile memories in parallel, and issues table read requests for reading the address tables and data read requests for reading the data to the nonvolatile memories in response to read commands from a host. When a table read request and a data read request are issued to a same nonvolatile memory, the control unit processes the data read request in priority to the table read request. | 02-05-2015 |