Patent application number | Description | Published |
20080267060 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING HIGH SPEED FAULT TRACING WITHIN A BLADE CENTER SYSTEM - Providing high speed fault tracing within a blade center system by using a high speed transmitter port of a switch to implement a first snoop port and using a high speed receiver port of the switch to implement a second snoop port, thus permitting snooping of the blade center system from a single blade slot. | 10-30-2008 |
20080267192 | SYSTEMS AND METHODS FOR MONITORING HIGH SPEED NETWORK TRAFFIC VIA SEQUENTIALLY MULTIPLEXED DATA STREAMS - Systems and methods for monitoring high-speed network traffic via sequentially multiplexed data streams. Exemplary embodiments include a switch module system, including a first switch module configured to be coupled to a first, server chassis, a first data port disposed on the first switch module and a set of first port data links configured to be coupled to a set of data port data links, each data link configurable to channel at least one of a normal data stream and a monitored data stream. | 10-30-2008 |
20080270638 | SYSTEMS AND METHODS FOR MONITORING HIGH SPEED NETWORK TRAFFIC VIA SIMULTANEOUSLY MULTIPLEXED DATA STREAMS - Systems and methods for monitoring high-speed network traffic via simultaneously multiplexed data streams. Exemplary embodiments include a switch module system, including a first switch module coupled to a first server chassis, a first data port disposed on the first switch module and a set of data links disposed on the first data port, each data link configurable to receive a normal data stream and a monitored data stream. | 10-30-2008 |
20110242692 | DATA-DEPENDENT NOISE-PREDICTIVE MAXIMUM LIKELIHOOD DETECTION (DD-NPML) FOR MAGNETIC RECORDING - In one embodiment, a method includes applying one or more whitening filters to an input stream of digitized samples from a magnetic data channel to produce a filtered sequence, performing one or more branch metric calculations to the filtered sequence to produce a branch metric, and applying a multi-state data-dependent noise-predictive maximum likelihood (DD-NPML) detector to the branch metric to produce an output stream. In another embodiment, a multi-channel data storage system includes a head for reading data from a storage medium, logic for applying one or more whitening filters to an input stream of digitized samples from a magnetic data channel to produce a filtered sequence, logic for performing one or more branch metric calculations to the filtered sequence to produce a branch metric, and logic for applying a multi-state DD-NPML detector to the branch metric to produce an output stream. Other systems and methods are described as well. | 10-06-2011 |
20130335845 | ADAPTIVE SOFT-OUTPUT DETECTOR FOR MAGNETIC TAPE READ CHANNELS - In one embodiment, a data storage system includes a tape channel for reading data from a tape to produce a signal, an adaptive noise whitening filter adapted for receiving the signal, the noise whitening filter being adapted for minimizing variance of noise affecting the signal output from the noise whitening filter, a soft DMAX detector adapted for receiving the signal from the noise whitening filter, the soft detector adapted for calculating first soft information about each bit of the signal and sending the first soft information to a soft decoder, and the soft decoder positioned subsequent to the soft detector, the soft decoder being adapted for calculating second soft information about each bit of the signal and sending the second soft information to the soft DMAX detector, wherein one or more noise whitening coefficients used in the noise whitening filter are updated using a noise whitening filter coefficient updater. | 12-19-2013 |
20130335846 | ADAPTIVE SOFT-OUTPUT DETECTOR FOR MAGNETIC TAPE READ CHANNELS - In accordance with one embodiment, a data storage system includes a tape channel for reading precoded data from a magnetic tape medium to produce a signal, a soft detector adapted for calculating first soft information about each bit of the signal and sending the first soft information to a soft decoder, and the soft decoder positioned subsequent to the soft detector, the soft decoder being adapted for calculating second soft information about each bit of the signal and sending the second soft information to the soft detector, wherein the precoded data includes a characteristic of being passed through at least one precoder prior to being written to the magnetic tape medium, and wherein the soft detector provides automatic compensation for the precoded data. Other systems, methods, and computer program products for reading data using an adaptive soft-output detector are described according to more embodiments. | 12-19-2013 |
20130335848 | ADAPTIVE SOFT-OUTPUT DETECTOR FOR MAGNETIC TAPE READ CHANNELS - In one embodiment, a data storage system includes a tape channel for reading data from a magnetic tape medium to produce a signal, a noise whitening filter positioned subsequent to the tape channel adapted for receiving the signal, wherein the noise whitening filter is adapted for minimizing variance of its output signal, a soft detector adapted for receiving output from the noise whitening filter, the soft detector adapted for calculating first soft information about each bit of the signal and sending the first soft information to a soft decoder, and the soft decoder positioned subsequent to the soft detector, the soft decoder being adapted for calculating second soft information about each bit of the signal and sending the second soft information to the soft detector. Other systems, methods, and computer program products are described according to more embodiments. | 12-19-2013 |
20130335849 | ADAPTIVE SOFT-OUTPUT DETECTOR FOR MAGNETIC TAPE READ CHANNELS - In one embodiment, a system includes a tape channel for reading data from a magnetic tape medium to produce a signal, a bank of noise whitening filters positioned subsequent to the tape channel adapted for receiving the signal, the bank of noise whitening filters being adapted for minimizing variance of noise affecting the signal at an output of the bank of noise whitening filters, wherein each noise whitening filter in the bank of noise whitening filters is dependent on a different possible data pattern, a soft DMAX detector adapted for calculating first soft information, dependent on the different possible data patterns, about each bit of the signal from the bank of noise whitening filters, and sending the first soft information to a soft decoder adapted for calculating second soft information about each bit of the signal and sending the second soft information to the soft DMAX detector. | 12-19-2013 |
Patent application number | Description | Published |
20080263255 | Apparatus, System, and Method For Adapter Card Failover - An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure. | 10-23-2008 |
20080263391 | Apparatus, System, and Method For Adapter Card Failover - An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure. | 10-23-2008 |
20080301345 | MULTI-CHARACTER ADAPTER CARD - One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data. | 12-04-2008 |
20090006809 | NON-DISRUPTIVE CODE UPDATE OF A SINGLE PROCESSOR IN A MULTI-PROCESSOR COMPUTING SYSTEM - Updating code of a single processor in a multi-processor system includes halting transactions processed by a first processor in the system and processing of transactions by a second processor in the system are maintained. The first processor then receives new code and an operating system running on the first processor is terminated whereby all processes and threads being executed by the first processor are terminated. Execution of a self-reset of the first processor is commenced and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor. | 01-01-2009 |
20100312942 | Redundant and Fault Tolerant control of an I/O Enclosure by Multiple Hosts - An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure. | 12-09-2010 |
20110087837 | SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING - A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein. | 04-14-2011 |
20120084514 | LOCKING A CACHE LINE FOR WRITE OPERATIONS ON A BUS - Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line. | 04-05-2012 |
20120096469 | SYSTEMS AND METHODS FOR DYNAMICALLY SCANNING A PLURALITY OF ACTIVE PORTS FOR WORK - Systems and methods for scanning ports for work are provided. One system includes one or more processors, multiple ports, a first tracking mechanism, and a second tracking mechanism for tracking high priority work and low priority work, respectively. The processor(s) is/are configured to perform the below method. One method includes scanning the ports, finding high priority work on a port, and accepting or declining the high priority work. The method further includes changing a designation of the processor to TRUE in the first tracking mechanism if the processor accepts the high priority work such that the processor is allowed to perform the high priority work on the port. Also provided are computer storage mediums including computer code for performing the above method. | 04-19-2012 |
20120191904 | SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING - A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein. | 07-26-2012 |
20120254654 | METHOD AND SYSTEM FOR USING A STANDBY SERVER TO IMPROVE REDUNDANCY IN A DUAL-NODE DATA STORAGE SYSTEM - Methods are provided in which a standby server, a first main server, and a second main server to control shared input/output (I/O) adapters in a storage system are provided. The standby server is in communication with the first main server and the second main server, and the storage system is configured to operate as a dual node active system. The methods include activating the standby server in response to receiving a communication from the first main server of a fail mode of the second main server. Systems and physical computer storage media are also provided. | 10-04-2012 |
20130111106 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE | 05-02-2013 |
20130111131 | DYNAMICALLY ADJUSTED THRESHOLD FOR POPULATION OF SECONDARY CACHE | 05-02-2013 |
20130111133 | DYNAMICALLY ADJUSTED THRESHOLD FOR POPULATION OF SECONDARY CACHE | 05-02-2013 |
20130111134 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS | 05-02-2013 |
20130111146 | SELECTIVE POPULATION OF SECONDARY CACHE EMPLOYING HEAT METRICS | 05-02-2013 |
20130145206 | METHOD AND SYSTEM FOR USING A STANDBY SERVER TO IMPROVE REDUNDANCY IN A DUAL-NODE DATA STORAGE SYSTEM - A standby server, a first main server, and a second main server to control shared input/output (I/O) adapters in a storage system are provided. The standby server is in communication with the first main server and the second main server, and the storage system is configured to operate as a dual node active system. The standby server is activated in response to receiving a communication from the first main server of a fail mode of the second main server. Systems and physical computer storage media are also provided. | 06-06-2013 |
20130185512 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS - For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes. | 07-18-2013 |
20130205077 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE - For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. | 08-08-2013 |
20130232294 | ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM - Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache. | 09-05-2013 |
20130232295 | ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM - Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache. | 09-05-2013 |
20130346538 | MANAGING CACHE MEMORIES - A method for managing cache memories includes providing a computerized system including a shared data storage system (CS) configured to interact with several local servers that serve applications using respective cache memories, and access data stored in the shared data storage system; providing cache data information from each of the local servers to the shared data storage system, the cache data information comprising cache hit data representative of cache hits of each of the local servers, and cache miss data representative of cache misses of each of the local servers; aggregating, at the shared data storage system, at least part of the cache hit and miss data received and providing the aggregated cache data information to one or more of the local servers; and at the local servers, updating respective one or more cache memories used to serve respective one or more applications based on the aggregated cache data information. | 12-26-2013 |
20140201448 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS - For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. | 07-17-2014 |
20150046656 | MANAGING AND SHARING STORAGE CACHE RESOURCES IN A CLUSTER ENVIRONMENT - Systems and methods are provided for managing storage cache resources among all servers within the cluster storage environment. A method includes partitioning a main cache of a corresponding node into a global cache and a local cache, sharing each global cache of each node with other ones of the nodes of the multiple nodes, and dynamically adjusting a ratio of an amount of space of the main cache making up the global cache and an amount of space of the main cache making up the local cache, based on access latency and cache hit over a predetermined period of time of each of the global cache and the local cache. | 02-12-2015 |