Patent application number | Description | Published |
20100197102 | FILM DEPOSITION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A film deposition method includes the steps of: coating a solution containing a polysilane compound on a substrate to form a coating film and then carrying out a first thermal treatment in an inert atmosphere, thereby forming the coating film into a silicon film; forming a coating film containing a polysilane compound on the silicon film and then carrying out a second thermal treatment in an inert atmosphere or a reducing atmosphere, thereby forming the coating film into a silicon oxide precursor film; and carrying out a third thermal treatment in an oxidizing atmosphere, thereby forming the silicon oxide precursor film into a silicon oxide film and simultaneously densifying the silicon film. | 08-05-2010 |
20130135749 | LIGHT REFLECTING MEMBER, LIGHT BEAM EXTENSION DEVICE, IMAGE DISPLAY DEVICE, AND OPTICAL DEVICE - An image display device includes an image generating device, a light guide unit which includes a light guide plate and first and second deflection sections, and a light beam extension device which extends light incident from the image generating device, along a Z direction when an incident direction of light incident on the light guide plate is set to be an X direction and a direction of propagation of light in the light guide plate is set to be a Y direction, and emits the light to the light guide unit, wherein the light beam extension device includes a first reflecting mirror on which light from the image generating device is incident, and a second reflecting mirror which emits light incident from the first reflecting mirror to the light guide unit, and each of the first and second reflecting mirrors has a light reflecting surface having a sawtooth-shaped cross-sectional shape. | 05-30-2013 |
Patent application number | Description | Published |
20080263228 | Single-chip microcomputer - A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced. | 10-23-2008 |
20080294873 | Microcomputer - A built-in memory is divided into the following two types: first memories | 11-27-2008 |
20080313444 | MICROCOMPUTER AND DIVIDING CIRCUIT - Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits. | 12-18-2008 |
20100191934 | MICROCOMPUTER AND DIVIDING CIRCUIT - Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits. | 07-29-2010 |
20120023281 | Single-chip microcomputer - A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced. | 01-26-2012 |