Patent application number | Description | Published |
20110068715 | LED Light Sources with Improved Thermal Compensation - A compound light source that compensates for changes in electrical conversion efficiency with increasing operating temperature is disclosed. The compound light source generates light of a design intensity at a design temperature in response to a drive current flowing through the light source. The light source includes a primary light source and a compensating light source. The primary and compensating light sources convert an electrical current passing therethrough to light, each light source being characterized by an electrical conversion efficiency that decreases with increasing temperature and that also decreases with increasing current. The compound light source includes a temperature sensor that measures the temperature of the primary light source and a current splitting circuit that divides the drive current between the primary and compensating light sources to compensate for the decrease in efficiency of the primary light source with temperature above the design temperature. | 03-24-2011 |
20110254027 | METHOD FOR CONTROLLING COLOR ACCURACY IN A LIGHT-EMITTING SEMICONDUCTOR-BASED DEVICE AND PROCESS FOR PRODUCING A LIGHT-EMITTING SEMICONDUCTOR-BASED DEVICE WITH CONTROLLED COLOR ACCURACY - A method for controlling color accuracy of a light-emitting semiconductor-based device, and a process for producing a light-emitting semiconductor-based device with desired color accuracy is disclosed. The color accuracy is controlled by defining a desired color accuracy of a light produced by mixing colors emitted by at least two light sources over a first range of operating conditions; determining characteristics of the light as a function of operating conditions; and establishing desired light characteristics of the at least two light sources over a second range of operating condition in accordance with the step of defining and the step of determining. | 10-20-2011 |
20120012865 | LED ARRAY PACKAGE WITH A HIGH THERMALLY CONDUCTIVE PLATE - A light source includes a substrate, a light emitting diode on the substrate, and a plate supporting member attached to the substrate and surrounding the light emitting diode to form a cavity. In addition, the light source includes a plate on the plate supporting member such that a distance between the plate and the substrate is approximately less than or equal to 1 mm. Furthermore, the light source includes a phosphor layer on the plate opposite the cavity. | 01-19-2012 |
20120133289 | AC LED Light Source with Reduced Flicker - A lighting apparatus and method for operating LED-based lighting devices are disclosed. The apparatus includes a receiver that receives a potential from a power source whose output varies as a function of time, an energy storage device, and an LED array. The energy storage device stores energy from the power source when the driving potential is greater than a predetermined value. The LED array has variable forward bias potential, the LED array generating light when a potential across the array is greater than the selected forward bias potential. A source selector connects the energy storage device to the array when the potential from the power source is less than a predetermined value. A controller that varies the forward bias potential such that the difference between the forward bias potential and potential across the array is maintained at a value less than a predetermined value. | 05-31-2012 |
Patent application number | Description | Published |
20100133556 | LED ARRAY PACKAGE COVERED WITH A HIGHLY THERMAL CONDUCTIVE PLATE - A light source includes a substrate, a light emitting diode on the substrate, and a phosphor layer over the light emitting diode. A plate is on the phosphor layer. An attachment member is coupled to the plate and is configured to conduct heat away from the plate. | 06-03-2010 |
20100231135 | Reconfigurable LED Array and Use in Lighting System - A light-emitting device capable of being powered by an AC power supply or an unregulated DC power supply is disclosed. The light-emitting device, in an aspect, is coupled to a controller, a light-emitting diode (“LED”) array, and a power supply, wherein the power supply can be an AC power source or an unregulated DC power source. While the power supply provides electrical power, the controller generates various LED control signals in response to power fluctuation of the electrical power. The LED array allows at least a portion of LEDs to be activated in accordance with the logic states of the LED control signals. | 09-16-2010 |
20110169417 | Reconfigurable LED Array and Use in Lighting System - A light-emitting device capable of being powered by an AC power supply or an unregulated DC power supply is disclosed. The light-emitting device, in an aspect, is coupled to a controller, a light-emitting diode (“LED”) array, and a power supply, wherein the power supply can be an AC power source or an unregulated DC power source. While the power supply provides electrical power, the controller generates various LED control signals in response to power fluctuation of the electrical power. The LED array allows at least a portion of LEDs to be activated in accordance with the logic states of the LED control signals. | 07-14-2011 |
20110181194 | Reconfigurable LED Array and Use in Lighting System - A light-emitting device capable of being powered by an AC power supply or an unregulated DC power supply is disclosed. The light-emitting device, in an aspect, is coupled to a controller, a light-emitting diode (“LED”) array, and a power supply, wherein the power supply can be an AC power source or an unregulated DC power source. While the power supply provides electrical power, the controller generates various LED control signals in response to power fluctuation of the electrical power. The LED array allows at least a portion of LEDs to be activated in accordance with the logic states of the LED control signals. | 07-28-2011 |
Patent application number | Description | Published |
20110068697 | Phosphor Converted Light Source Having an Additional LED to Provide Long Wavelength Light - A light source having first and second LEDs and a phosphor layer that converts light generated by the first LED is disclosed. The first LED emits light at a first wavelength. The layer of phosphor is illuminated by the first LED, the phosphor being excited by light of the first wavelength to convert light of the first wavelength to a band of wavelengths having wavelengths between the first wavelength and a second wavelength. The second LED emits light at a third wavelength that is greater than the first wavelength. The phosphor is not substantially excited by light of the third wavelength. The combined light from the phosphor, and first and second LEDs is perceived as being white by a human observer. | 03-24-2011 |
20110069502 | Mounting Fixture for LED Lighting Modules - A mounting fixture for a light-emitting device such as an LED is disclosed. The fixture includes a base having a cavity adapted to receive a module having a light-emitting device mounted thereon, a cover, power contacts that provide electrical connections to the light-emitting device, a spring and a closure. The base has a heat-conducting surface. The cover has a window positioned to allow light from the light-emitting device to pass through the window. The first and second power contacts have first and second portions, respectively, adapted to receive external power connections on an outer surface of the mounting fixture. The spring forces the module against the heat-conducting surface when the base is in a closed position relative to the cover, the module being manually removable from the base when the cover is in an open position relative to the base. The closure reversibly attaches the base to the cover. | 03-24-2011 |
20110073878 | LED ARRAY PACKAGE COVERED WITH A HIGHLY THERMAL CONDUCTIVE PLATE - A light source includes a substrate, a light emitting diode on the substrate, and a phosphor layer over the light emitting diode. A plate is on the phosphor layer. An attachment member is coupled to the plate and is configured to conduct heat away from the plate. | 03-31-2011 |
Patent application number | Description | Published |
20090019306 | Protecting tag information in a multi-level cache hierarchy - In one embodiment, the present invention includes a shared cache memory that is inclusive with other cache memories coupled to it. The shared cache memory includes error correction logic to correct an error present in a tag array of one of the other cache memories and to provide corrected tag information to replace a tag entry in the tag array including the error. Other embodiments are described and claimed. | 01-15-2009 |
20090077360 | Software constructed stands for execution on a multi-core architecture - In one embodiment, the present invention includes a software-controlled method of forming instruction strands. The software may include instructions to obtain code of a superblock including a plurality of basic blocks, build a dependency directed acyclic graph (DAG) for the code, sort nodes coupled by edges of the dependency DAG into a topological order, form strands from the nodes based on hardware constraints, rule constraints, and scheduling constraints, and generate executable code for the strands and store the executable code in a storage. Other embodiments are described and claimed. | 03-19-2009 |
20090222654 | Distribution of tasks among asymmetric processing elements - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system. | 09-03-2009 |
20090328057 | SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX - A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied. | 12-31-2009 |
20100037036 | METHOD TO IMPROVE BRANCH PREDICTION LATENCY - An apparatus to generate a branch prediction of an instruction based at least in part on the address of the previous branch instruction, wherein the previous instruction is prior to the instruction in a program order. The prediction can also based on a branch history value with respect to the previous branch instruction and one or more previous branch predictions. | 02-11-2010 |
20110161632 | COMPILER ASSISTED LOW POWER AND HIGH PERFORMANCE LOAD HANDLING - A method and apparatus for handling low power and high performance loads is herein described. Software, such as a compiler, is utilized to identify producer loads, consumer reuse loads, and consumer forwarded loads. Based on the identification by software, hardware is able to direct performance of the load directly to a load value buffer, a store buffer, or a data cache. As a result, accesses to cache are reduced, through direct loading from load and store buffers, without sacrificing load performance. | 06-30-2011 |
20130246712 | Methods And Apparatuses For Efficient Load Processing Using Buffers - Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads. | 09-19-2013 |
20130314425 | DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system | 11-28-2013 |
20130318373 | DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system | 11-28-2013 |
20130318374 | DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system | 11-28-2013 |
20140019656 | DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system | 01-16-2014 |
20140130058 | DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system. | 05-08-2014 |
20150012731 | DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system. | 01-08-2015 |
20150012765 | DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system. | 01-08-2015 |
20150012766 | DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS - Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system. | 01-08-2015 |
Patent application number | Description | Published |
20110154002 | Methods And Apparatuses For Efficient Load Processing Using Buffers - Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads. | 06-23-2011 |
20120079214 | ALLOCATION AND WRITE POLICY FOR A GLUELESS AREA-EFFICIENT DIRECTORY CACHE FOR HOTLY CONTESTED CACHE LINES - Methods and apparatus relating to allocation and/or write policy for a glueless area-efficient directory cache for hotly contested cache lines are described. In one embodiment, a directory cache stores data corresponding to a caching status of a cache line. The caching status of the cache line is stored for each of a plurality of caching agents in the system. An write-on-allocate policy is used for the directory cache by using a special state (e.g., snoop-all state) that indicates one or more snoops are to be broadcasted to all agents in the system. Other embodiments are also disclosed. | 03-29-2012 |
20130185522 | ALLOCATION AND WRITE POLICY FOR A GLUELESS AREA-EFFICIENT DIRECTORY CACHE FOR HOTLY CONTESTED CACHE LINES - Methods and apparatus relating to allocation and/or write policy for a glueless area-efficient directory cache for hotly contested cache lines are described. In one embodiment, a directory cache stores data corresponding to a caching status of a cache line. The caching status of the cache line is stored for each of a plurality of caching agents in the system. An write-on-allocate policy is used for the directory cache by using a special state (e.g., snoop-all state) that indicates one or more snoops are to be broadcasted to all agents in the system. Other embodiments are also disclosed. | 07-18-2013 |
20140112339 | HIGH PERFORMANCE INTERCONNECT - A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state | 04-24-2014 |
20140181394 | DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS - Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor. | 06-26-2014 |
20140189239 | PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES - A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed. | 07-03-2014 |
20140189417 | APPARATUS AND METHOD FOR PARTIAL MEMORY MIRRORING - An apparatus and method are described for performing partial memory mirroring operations. For example, one embodiment of a processor comprises: a processor core for generating a read or write transaction having a system memory address; a home agent identified to service the read or write transaction based on the system memory address; one or more target address decoders (TADs) associated with the home agent to determine whether the system memory address is within a mirrored memory region or a non-mirrored memory region, wherein: if the system memory address is within a mirrored memory region, then the one or more TADs identifying multiple mirrored memory channels for the read or write transaction; and if the system memory address is not within a mirrored memory region, then the one or more TADs identifying a single memory channel for the read or write transaction. | 07-03-2014 |
20140201463 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback. | 07-17-2014 |
20150081984 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback. | 03-19-2015 |
Patent application number | Description | Published |
20080262587 | EXTENDABLE AND RETRACTABLE LEAD HAVING A SNAP-FIT TERMINAL CONNECTOR - A lead having an extendable and retractable fixation mechanism has a rotating terminal pin at the terminal end which rotates the fixation mechanism at the distal end. As the terminal pin is rotated, the fixation mechanism is extended or retracted from the distal end of the lead. A threaded collar allows for the fixation mechanism to smoothly extend and retract from the lead, and allows for a 1:1 turn ratio between the terminal pin and the fixation mechanism. A fluoroscopic ring disposed at the distal end of the lead provides information during the implantation process. | 10-23-2008 |
20090048652 | MEDICAL DEVICE HAVING PLASMA POLYMERIZED COATING AND METHOD THEREFOR - A medical device having at least one plasma polymerized coating allowing for a first component to be coupled with a second component. | 02-19-2009 |
20100075018 | SURFACE MODIFICATION TO IMPROVE LUBRICITY, ABRASION RESISTANCE AND TEMPERATURE RESILIENCE OF LEADS - A medical electrical lead body having an outer surface and including at least one lumen having an inner surface treated with a silane surface modifying agent to form a three-dimensional, densely cross-linked lubricious coating over at least a portion of the inner surface of the lumen. The outer surface of the lead body also may be similarly treated. The lubricious silane coating may reduce the coefficient of friction of the coated surface of the lead body by as much as 80% when compared to an uncoated surface. A reduction in the coefficient of friction may enhance the stringing efficiency of a conductor through the lead body lumen and may enhance its abrasion resistance. | 03-25-2010 |
20110052787 | SOLVENTLESS METHOD FOR FORMING A COATING ON A MEDICAL ELECTRICAL LEAD BODY - A solventless method for forming a coating on a medical electrical lead is described. The method includes combining particles of a therapeutic agent with a polymeric material in a flowable form in the absence of a solvent to form a uniform suspension. A predetermined amount of the suspension is dispensed onto a portion of the lead and is then cured to form the therapeutic agent eluting layer. Additional layers such as a primer layer, fluoro-opaque layer and/or a topcoat layer can be formed using the solventless method. Employing a solventless method may avoid contraction of the layer being formed due to solvent evaporation during the curing process, and may facilitate greater control over the thickness of the therapeutic agent eluting coating. | 03-03-2011 |
20130122185 | SURFACE MODIFICATION TO IMPROVE LUBRICITY, ABRASION RESISTANCE AND TEMPERATURE RESILIENCE OF LEADS - A medical electrical lead body having an outer surface and including at least one lumen having an inner surface treated with a silane surface modifying agent to form a three-dimensional, densely cross-linked lubricious coating over at least a portion of the inner surface of the lumen. The outer surface of the lead body also may be similarly treated. The lubricious silane coating may reduce the coefficient of friction of the coated surface of the lead body by as much as 80% when compared to an uncoated surface. A reduction in the coefficient of friction may enhance the stringing efficiency of a conductor through the lead body lumen and may enhance its abrasion resistance. | 05-16-2013 |