Sasago
Masaru Sasago, Toyama JP
Patent application number | Description | Published |
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20130260293 | PHOTOMASK, AND PATTERN FORMATION METHOD AND EXPOSURE APPARATUS USING THE PHOTOMASK - A photomask includes a translucent substrate; and a light-shielding film formed on the translucent substrate, and including a light-shielding portion and an opening which serves as a translucent region. A plurality of recesses are formed in a region of the translucent substrate, which is exposed from the opening. Widths of the plurality of recesses gradually increase with an increase in distances from a focal point so that light transmitted by the plurality of recesses is focused in a predetermined position. | 10-03-2013 |
20140327157 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip. | 11-06-2014 |
Yoshitaka Sasago, Tokyo JP
Patent application number | Description | Published |
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20080261365 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A technology realizing decreases of capacitance between the adjoining floating gates and of the threshold voltage shift caused by interference between the adjoining memory cells in a nonvolatile semiconductor memory device with the advances of miniaturization in the period following the 90 nm generation. By having the floating gate | 10-23-2008 |
20140218999 | SEMICONDUCTOR STORAGE DEVICE - With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines ( | 08-07-2014 |
20140246646 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF FABRICATING SAME - A memory cell array having such a structure that can be realized with a simpler process and ideal for realizing a higher density is provided. Memory cells have a structure in which channel layers ( | 09-04-2014 |
Yoshitska Sasago, Tachikawa JP
Patent application number | Description | Published |
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20110273927 | SEMICONDUCTOR DEVICE - A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA). | 11-10-2011 |
20110297911 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser. | 12-08-2011 |