Patent application number | Description | Published |
20090134471 | SEMICONDUCTOR INTERCONNECT - One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed. | 05-28-2009 |
20090258471 | Application of Different Isolation Schemes for Logic and Embedded Memory - The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic. | 10-15-2009 |
20100163997 | EPITAXIAL DEPOSITION-BASED PROCESSES FOR REDUCING GATE DIELECTRIC THINNING AT TRENCH EDGES AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface. The epitaxial comprising silicon layer is oxidized to convert at least a portion into a thermally grown silicon oxide layer, wherein the thermally grown silicon oxide layer provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges. Fabrication of the IC is then completed. | 07-01-2010 |
20100164004 | METHODS FOR REDUCING GATE DIELECTRIC THINNING ON TRENCH ISOLATION EDGES AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges to the silicon including surface, and fabrication is then completed. | 07-01-2010 |
20100274506 | METHOD FOR MEASURING INTERFACE TRAPS IN THIN GATE OXIDE MOSFETS - A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points. | 10-28-2010 |
20120112275 | Drain Extended CMOS with Counter-Doped Drain Extension - An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region. | 05-10-2012 |
20120275207 | SRAM CELL PARAMETER OPTIMIZATION - An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided. | 11-01-2012 |
20140001526 | Analog Floating-Gate Capacitor with Improved Data Retention in a Silicided Integrated Circuit | 01-02-2014 |
20140021545 | POCKET COUNTERDOPING FOR GATE-EDGE DIODE LEAKAGE REDUCTION - A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions. | 01-23-2014 |
20140042545 | MOS TRANSISTORS HAVING REDUCED LEAKAGE WELL-SUBSTRATE JUNCTIONS - A Metal-Oxide Semiconductor (MOS) transistor includes a substrate having a topside semiconductor surface doped with a first dopant type having a baseline doping level. A well is formed in the semiconductor surface doped with a second doping type. The well forms a well-substrate junction having a well depletion region. A retrograde doped region is below the well-substrate junction doped with the first dopant type having a peak first dopant concentration of between five (5) and one hundred (100) times above the baseline doping level at a location of the peak first dopant concentration, wherein with zero bias across the well-substrate junction at least (>) ninety (90) % of a total dose of the retrograde doped region is below the bottom of the well depletion region. A gate structure is on the well. Source and drain regions are on opposing sides of the gate structure. | 02-13-2014 |
20140061785 | Drain Extended CMOS with Counter-Doped Drain Extension - An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region. | 03-06-2014 |
20140070361 | DIFFUSION RESISTOR WITH REDUCED VOLTAGE COEFFICIENT OF RESISTANCE AND INCREASED BREAKDOWN VOLTAGE USING CMOS WELLS - Integrated circuits and manufacturing methods are presented for creating diffusion resistors ( | 03-13-2014 |
20140103440 | I-SHAPED GATE ELECTRODE FOR IMPROVED SUB-THRESHOLD MOSFET PERFORMANCE - Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction. | 04-17-2014 |
20140124828 | ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION - A semiconductor controlled rectifier (FIG. | 05-08-2014 |
20140183630 | DECMOS FORMED WITH A THROUGH GATE IMPLANT - An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor. | 07-03-2014 |
20140183655 | HIGH PERFORMANCE ISOLATED VERTICAL BIPOLAR JUNCTION TRANSISTOR AND METHOD FOR FORMING IN A CMOS INTEGRATED CIRCUIT - A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types. | 07-03-2014 |
20140252485 | Low-Cost CMOS Structure with Dual Gate Dielectrics and Method of Forming the CMOS Structure - Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor. | 09-11-2014 |
20140295631 | ANALOG FLOATING-GATE CAPACITOR WITH IMPROVED DATA RETENTION IN A SILICIDED INTEGRATED CIRCUIT - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate. | 10-02-2014 |
20150187760 | DEEP COLLECTOR VERTICAL BIPOLAR TRANSISTOR WITH ENHANCED GAIN - An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant. | 07-02-2015 |
20150187938 | LOW COST DEMOS TRANSISTOR WITH IMPROVED CHC IMMUNITY - An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate. | 07-02-2015 |
20150249040 | LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING THE CMOS STRUCTURE - Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor. | 09-03-2015 |
20150249088 | LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING THE CMOS STRUCTURE - Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor. | 09-03-2015 |
20150294967 | ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION - A semiconductor controlled rectifier (FIG. | 10-15-2015 |
Patent application number | Description | Published |
20110146985 | Proppant Having A Glass-Ceramic Material - The present invention relates to glass-ceramic proppants which can be used to prop open subterranean formation fractions, as well as other uses. Proppant formulations are further disclosed which use one or more proppants of the present invention. Methods to prop open subterranean formation fractions are further disclosed. In addition, other uses for the proppants of the present invention are further disclosed, as well as methods of making the glass-ceramic proppants. | 06-23-2011 |
20110160104 | Ceramic Particles With Controlled Pore and/or Microsphere Placement and/or Size and Method Of Making Same - The present invention relates to lightweight high strength microsphere containing ceramic particles having controlled microsphere placement and/or size and microsphere morphology, which produces an improved balance of specific gravity and crush strength such that they can be used in applications such as proppants to prop open subterranean formation fractions. Proppant formulations are further disclosed which use one or more microsphere containing ceramic particles of the present invention. Methods to prop open subterranean formation fractions are further disclosed. In addition, other uses for the microsphere containing ceramic particles of the present invention are further disclosed, as well as methods of making the microsphere containing ceramic particles. | 06-30-2011 |
20130206408 | Light Weight Proppant With Improved Strength And Methods Of Making Same - Methods are described to make strong, tough, and/or lightweight glass-ceramic composites having a crystalline phase and an amorphous phase generated by viscous reaction sintering of a complex mixture of oxides and other materials. The present invention further relates to strong, tough, and lightweight glass-ceramic composites that can be used as proppants and for other uses. | 08-15-2013 |
20140249058 | Ceramic Particles With Controlled Pore And/Or Microsphere Placement And/Or Size And Method Of Making Same - The present invention relates to lightweight high strength microsphere containing ceramic particles having controlled microsphere placement and/or size and microsphere morphology, which produces an improved balance of specific gravity and crush strength such that they can be used in applications such as proppants to prop open subterranean formation fractions. Proppant formulations are further disclosed which use one or more microsphere containing ceramic particles of the present invention. Methods to prop open subterranean formation fractions are further disclosed. In addition, other uses for the microsphere containing ceramic particles of the present invention are further disclosed, as well as methods of making the microsphere containing ceramic particles. | 09-04-2014 |
Patent application number | Description | Published |
20120157358 | Self-Toughened High-Strength Proppant and Methods Of Making Same - Methods are described to make strong, tough, and lightweight whisker-reinforced glass-ceramic composites through a self-toughening structure generated by viscous reaction sintering of a complex mixture of oxides. The present invention further relates to strong, tough, and lightweight glass-ceramic composites that can be used as proppants and for other uses. | 06-21-2012 |
20120181020 | Method Of Manufacture And The Use Of A Functional Proppant For Determination Of Subterranean Fracture Geometries - Proppants having added functional properties are provided, as are methods that use the proppants to track and trace the characteristics of a fracture in a geologic formation. Information obtained by the methods can be used to design a fracturing job, to increase conductivity in the fracture, and to enhance oil and gas recovery from the geologic formation. The functionalized proppants can be detected by a variety of methods utilizing, for example, an airborne magnetometer survey, ground penetrating radar, a high resolution accelerometer, a geophone, nuclear magnetic resonance, ultra-sound, impedance measurements, piezoelectric activity, radioactivity, and the like. Methods of mapping a subterranean formation are also provided and use the functionalized proppants to detect characteristics of the formation. | 07-19-2012 |
20120190597 | Extrusion Process For Proppant Production - An extrusion method and apparatus are described for producing ceramics, glass, glass-ceramics, or composites suitable for use as proppants. The method includes forming one or more green body materials, extruding the green body materials to form a green body extrudate, separating and shaping the green body extrudate into individual green bodies, and sintering the green bodies to form proppants. The apparatus includes a means for forming an intimate mixture of green body materials, means to produce a green body extrudate, means for separating and shaping the green body extrudate into individual green bodies, and means to sinter the green green bodies to form proppants. | 07-26-2012 |
20130014945 | Low Surface Friction Proppants - A proppant having low surface friction is described, which is useful in hydrocarbon recovery. Methods of making low surface friction proppants are further described, as well as uses thereof. | 01-17-2013 |
20130244914 | Light Weight Proppant With Improved Strength And Methods Of Making Same - Methods are described to make strong, tough, and lightweight whisker-reinforced glass-ceramic composites through a self-toughening structure generated by viscous reaction sintering of a complex mixture of oxides. The invention further relates to strong, tough, and lightweight glass-ceramic composites that can be used as proppants and for other uses. | 09-19-2013 |
20150368548 | Light Weight Proppant With Improved Strength And Methods Of Making Same - Methods are described to make strong, tough, and lightweight whisker-reinforced glass-ceramic composites through a self-toughening structure generated by viscous reaction sintering of a complex mixture of oxides. The invention further relates to strong, tough, and lightweight glass-ceramic composites that can be used as proppants and for other uses. | 12-24-2015 |
Patent application number | Description | Published |
20080299759 | Method to form a via - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 12-04-2008 |
20080299762 | Method for forming interconnects for 3-D applications - A method for forming an interconnect, comprising (a) providing a substrate ( | 12-04-2008 |
20090166888 | 3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD - A die-on-die assembly has a first die ( | 07-02-2009 |
20090170246 | FORMING A 3-D SEMICONDUCTOR DIE STRUCTURE WITH AN INTERMETALLIC FORMATION - A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer. | 07-02-2009 |
20090176366 | MICROPAD FORMATION FOR A SEMICONDUCTOR - A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips. | 07-09-2009 |
20090191708 | METHOD FOR FORMING A THROUGH SILICON VIA LAYOUT - A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields. | 07-30-2009 |
20100327440 | 3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD - A die-on-die assembly has a first die ( | 12-30-2010 |
20110151663 | METHOD TO FORM A VIA - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 06-23-2011 |
Patent application number | Description | Published |
20120038786 | Decreasing Image Acquisition Time for Compressive Imaging Devices - Mechanisms for increasing the rate of acquisition of compressed/encoded image representations are disclosed. An imaging system may deliver subsets of a modulated light stream onto respective light sensing devices. The light sensing devices may be sampled in parallel. Samples from each light sensing device may be used to construct a respective sub-image of a final image. The parallelism allows compressed images to be acquired at a higher rate. The number of light sensing devices and/or the number of pixels per image may be selected to achieve a target image acquisition rate. In another embodiment, spatial portions of the incident light stream are separated and delivered to separate light modulators. In yet another embodiment, the incident light stream is split into a plurality of beams, each of which retains the image present in the incident light stream and is delivered to a separate light modulator. | 02-16-2012 |
20120038789 | Determining Light Level Variation in Compressive Imaging by Injecting Calibration Patterns into Pattern Sequence - An imaging system and method that captures compressive sensing (CS) measurements of a received light stream, and also obtains samples of background light level (BGLL). The BGLL samples may be used to compensate the CS measurements for variations in the BGLL. The system includes: a light modulator to spatially modulate the received light stream with spatial patterns, and a lens to concentrate the modulated light stream onto a light detector. The samples of BGLL may be obtained in various ways: (a) injecting calibration patterns among the spatial patterns; (b) measuring complementary light reflected by digital micromirrors onto a secondary output path; (c) separating and measuring a portion of light from the optical input path; (d) low-pass filtering the CS measurements; and (e) employing a light power meter with its own separate input path. Also, the CS measurements may be high-pass filtered to attenuate background light variation. | 02-16-2012 |
20120038790 | Low-Pass Filtering of Compressive Imaging Measurements to Infer Light Level Variation - An imaging system and method that captures compressive sensing (CS) measurements of a received light stream, and also obtains samples of background light level (BGLL). The BGLL samples may be used to compensate the CS measurements for variations in the BGLL. The system includes: a light modulator to spatially modulate the received light stream with spatial patterns, and a lens to concentrate the modulated light stream onto a light detector. The samples of BGLL may be obtained in various ways: (a) injecting calibration patterns among the spatial patterns; (b) measuring complementary light reflected by digital micromirrors onto a secondary output path; (c) separating and measuring a portion of light from the optical input path; (d) low-pass filtering the CS measurements; and (e) employing a light power meter with its own separate input path. Also, the CS measurements may be high-pass filtered to attenuate background light variation. | 02-16-2012 |
20120038819 | TIR Prism to Separate Incident Light and Modulated Light in Compressive Imaging Device - A compressive imaging system including a light modulator, a light sensing device and a TIR prism. The TIR prism is configured to receive an incident light beam, to provide the incident light beam to the light modulator, to receive a modulated light beam MLB from the light modulator, and to direct the modulated light beam onto a sensing path. The light sensing device receives the modulated light beam (or at least a portion of the modulated light beam) and generates an electrical signal that represents intensity of the modulated light beam (or the “at least a portion” of the modulated light beam). The TIR prism may reduce a distance required to separate the incident light beam from the modulated light beam. | 02-16-2012 |
20130002858 | Mechanisms for Conserving Power in a Compressive Imaging System - A system and method for conserving power in compressive imaging. An optical subsystem separates an incident light stream into a primary light stream and a secondary light stream. The primary light stream is modulated with a sequence of spatial patterns by a light modulator. The modulated light stream is sensed by a first light sensing device. The secondary light stream is sensed by a second light sensing device. The signal(s) produced by the second light sensing device may be monitored to determine when to turn on power to the light modulator. Thus, the light modulator may remain off when not needed. In an alternative implementation, a light sensing device is used to sense the light reflected from the light modulator in its power-off state. The signal(s) produced by that light sensing device may be monitored to determine when to turn on power to the light modulator. | 01-03-2013 |
20140002721 | Dedicated Power Meter to Measure Background Light Level in Compressive Imaging System | 01-02-2014 |
20140009638 | Dual-Port Measurements of Light Reflected from Micromirror Array - An imaging system and method that captures compressive sensing (CS) measurements of a received light stream, and also obtains samples of background light level (BGLL). The BGLL samples may be used to compensate the CS measurements for variations in the BGLL. The system includes: a light modulator to spatially modulate the received light stream with spatial patterns, and a lens to concentrate the modulated light stream onto a light detector. The samples of BGLL may be obtained in various ways: (a) injecting calibration patterns among the spatial patterns; (b) measuring complementary light reflected by digital micromirrors onto a secondary output path; (c) separating and measuring a portion of light from the optical input path; (d) low-pass filtering the CS measurements; and (e) employing a light power meter with its own separate input path. Also, the CS measurements may be high-pass filtered to attenuate background light variation. | 01-09-2014 |