Patent application number | Description | Published |
20080215830 | EMPLOYING A DATA STRUCTURE OF READILY ACCESSIBLE UNITS OF MEMORY TO FACILITATE MEMORY ACCESS - A data structure of readily accessible units of memory is provided. The data structure includes designations of one or more units of memory that while represented in the data structure do not need expensive address translation, other tests or special handling in order to access the units of memory. By employing such a data structure, memory access and system performance are enhanced. | 09-04-2008 |
20080243465 | FACILITATING INPUT/OUTPUT PROCESSING OF ONE OR MORE GUEST PROCESSING SYSTEMS - An article of manufacture, method and system are provided for facilitating input/output (I/O) processing of at least one guest processing system. The article of manufacture includes at least one computer-usable medium having computer-readable program code logic to facilitate the I/O processing of the at least one guest processing system. The computer-readable program code logic when executing performing the following: emulating on a native system an I/O architecture for the at least one guest processing system, the emulating including: providing multiple device managers for a plurality of I/O devices of the I/O architecture; providing at least one communications adapter process interfacing the multiple device managers to the at least one network driver process; and wherein the multiple device managers translate I/O messages in at least one guest processing system format to messages in native system format for processing by the at least one communications adapter process, thereby facilitating I/O processing. | 10-02-2008 |
20080243468 | PROVIDING MEMORY CONSISTENCY IN AN EMULATED PROCESSING ENVIRONMENT - Memory consistency is provided in an emulated processing environment. A processor architected with a weak memory consistency emulates an architecture having a firm memory consistency. This memory consistency is provided without requiring serialization instructions or special hardware. | 10-02-2008 |
20080244328 | GENERALIZED TRACE AND LOG FACILITY FOR FIRST ERROR DATA COLLECTION - A generalized trace and log facility is employed to collect data, including data associated with the first occurrence of an error. The facility provides standardized application programming interfaces to be used to collect data, print the data, and forward the data to a support team, if desired. | 10-02-2008 |
20080244570 | FACILITATING COMMUNICATION WITHIN AN EMULATED PROCESSING ENVIRONMENT - Communication between processors and I/O communications processes is facilitated. During the communication, shared control blocks and input/output queues are updated without using locks. Instead, a lockless capability is provided to update the queues and control blocks, thereby enhancing system performance and minimizing the need for recovery processes. | 10-02-2008 |
20090083720 | EMPLOYING IDENTIFIERS PROVIDED BY AN OPERATING SYSTEM OF A PROCESSING ENVIRONMENT TO OPTIMIZE THE PROCESSING ENVIRONMENT - Optimizations are provided for processing environments. Selected memory objects are tagged with unique identifiers by an operating system of the environment, and those identifiers are used to manage processing within the environment. By detecting by a processing platform of the environment that a memory object has been tagged with a unique identifier, certain tasks may be bypassed and/or memory objects may be reused, even if located at a different location. | 03-26-2009 |
20110071813 | Page Mapped Spatially Aware Emulation of a Computer Instruction Set - Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page. | 03-24-2011 |
20110071814 | Self Initialized Host Cell Spatially Aware Emulation of a Computer Instruction Set - A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed | 03-24-2011 |
20110071815 | Host Cell Spatially Aware Emulation of a Guest Wild Branch - A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed. | 03-24-2011 |
20110071816 | Just In Time Compiler in Spatially Aware Emulation of a Guest Computer Instruction Set - A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell. | 03-24-2011 |
20110112820 | Reusing Invalidated Traces in a System Emulator - Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed. | 05-12-2011 |
20110202729 | EXECUTING ATOMIC STORE DISJOINT INSTRUCTIONS - A disjoint instruction for accessing operands in memory while executing in a processor of a plurality of processes interrogates a state indicator settable by other processors to determine if the disjoint instruction accessed the operands without an intervening store operation from another processor to the operand. A condition code is set based on the state indicator. | 08-18-2011 |
20140136179 | Page Mapped Spatially Aware Emulation of Computer Instruction Set - Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page. | 05-15-2014 |