Patent application number | Description | Published |
20110145452 | METHODS AND APPARATUS FOR DISTRIBUTION OF RAID STORAGE MANAGEMENT OVER A SAS DOMAIN - Methods and apparatus for distributing Redundant Array of Independent Disks (RAID) storage management to one or more Serial Attached SCSI (SAS) expanders in a SAS domain. A RAID set comprises a set of one or more SAS expanders coupled to communicate with one another to process I/O requests directed to a RAID logical volume of the RAID set. The RAID logical volume is distributed over portions of each of multiple storage devices. Each SAS expander of the RAID set is coupled to one or more of the multiple storage devices. Each SAS expander of the RAID set processes a corresponding portion of a received I/O request directed to the RAID logical volume. A master SAS expander of the RAID set receives and aggregates the status information from each of the SAS expanders of the RAID set and returns a completion status to the requesting SAS initiator. | 06-16-2011 |
20120173783 | SERIAL INPUT OUTPUT (SIO) PORT EXPANSION APPARATUS AND METHOD - An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to corresponding target devices coupled thereto and to receive returning split data streams from the target devices. The processor/controller splits the master data stream, based on its data, into a plurality of split data streams, and directs the split data streams to the target master ports based on the data in the split data streams. The processor/controller also assembles a plurality of returning split data streams into the returning master data stream and transmits the returning master data stream to the initiator device. | 07-05-2012 |
20120290875 | METHODS AND STRUCTURE FOR STORING ERRORS FOR ERROR RECOVERY IN A HARDWARE CONTROLLER - Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled. | 11-15-2012 |
20130179741 | MAPPING CIRCUIT TEST LOGIC BY ANALYZING REGISTER TRANSFER LEVEL CIRCUIT MODELS - Methods and systems for mapping and programming the debug logic of a circuit are provided. The system acquires a Register Transfer Level (RTL) representation of a circuit, wherein the circuit implements test logic that is externally programmable for providing one or more output signals corresponding to internal operational signals. The system analyzes the RTL representation to identify test multiplexers (MUXs) having registers for implementing the test logic, and correlates test register values for the test MUXs with outputs corresponding to the internal operational signals, based upon the RTL representation. The system further enables a user to select a desired internal operational signal for acquisition. Additionally, the system programs the test registers of the test MUXs of the circuit based on the correlated test register values to acquire the selected internal operational signal and to apply the acquired signal as one or more output signals. | 07-11-2013 |
20130257512 | METHODS AND STRUCTURE FOR UTILIZING EXTERNAL INTERFACES USED DURING NORMAL OPERATION OF A CIRCUIT TO OUTPUT TEST SIGNALS - Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit. The control unit receives the selected internal operational signals from the test signal routing hierarchy, and applies the selected internal operational signals to the external interface during normal operation of the integrated circuit. | 10-03-2013 |
20130262945 | METHODS AND STRUCTURE FOR CORRELATING MULTIPLE TEST OUTPUTS OF AN INTEGRATED CIRCUIT ACQUIRED DURING SEPARATE INSTANCES OF AN EVENT - Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event. | 10-03-2013 |
20130262946 | METHODS AND STRUCTURE FOR CORRELATION OF TEST SIGNALS ROUTED USING DIFFERENT SIGNALING PATHWAYS - Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals. | 10-03-2013 |