Patent application number | Description | Published |
20090193238 | Reconfigurable apparatus and method for providing multiple modes - A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided. The multi-mode providing apparatus includes: at least one reconfigurable operation mode execution unit performing a plurality of operations for processing a predetermined operation mode; a common coarse-grained array unit shared temporally by the at least one reconfigurable operation mode execution unit, and performing a main processing operation set to be performed by the common coarse-grained array unit, among the plurality of operations; and a controller determining whether the common coarse-grained array unit is available, and according to the result of the determination controlling the at least one reconfigurable operation mode execution unit so that the common coarse-grained array unit or an exclusive coarse-grained array unit performs the main processing operation, the exclusive coarse-grained array unit included in the at least one reconfigurable operation mode execution unit. Therefore, it is possible to reduce a delay time for data processing while reducing the size of hardware. | 07-30-2009 |
20120173598 | APPARATUS AND METHOD FOR DIVISION OF A GALOIS FIELD BINARY POLYNOMIAL - An apparatus and method for processing a division of a binary polynomial are provided. The apparatus includes a plurality of exclusive OR (XOR) operators that may perform a selective XOR operation with respect to a conditional bit of a dividend polynomial. The plurality of XOR operators may perform selective XOR operations in parallel and accordingly, a division of a binary polynomial may be rapidly performed. | 07-05-2012 |
20150305052 | COMMUNICATION NETWORK SETTING METHOD OF WIRELESS COMMUNICATION TERMINAL - According to a communication network setting method of a wireless communication terminal, wireless communication can be performed with a communication network by reading in advance features related to a communication standard or a communication provider for recognizing a wireless communication network accessible at a current place, detecting features from a wireless communication signal received at the current place, and then setting a modem in a hardware or software scheme according to the features. | 10-22-2015 |
Patent application number | Description | Published |
20110103781 | SHAKE CORRECTION APPARATUS IN DIGITAL CAMERA - A shake correction apparatus for correcting shake of a camera includes: a lens support plate including a correction lens and driven in a perpendicular direction with respect to an optical axis; and a position fixing member that decouplably couples with the lens support plate and fixes a position of the lens support plate according to a rotation of the lens support plate. | 05-05-2011 |
20120105960 | OPTICAL DEVICE INCLUDING ADJUSTABLE OPTICAL ELEMENT - An optical device includes an optical element through which light is transmitted, a frame that supports the optical element, magnets in the frame around the optical element, a base unit that movably supports the frame, a cover unit to cover the magnets, and magnetic force generating units in the cover unit in positions corresponding to the magnets and that generate magnetic force when an electrical signal is applied. | 05-03-2012 |
20130027524 | LIGHT AMOUNT ADJUSTING APPARATUS AND PHOTOGRAPHING APPARATUS INCLUDING THE SAME - A light amount adjusting apparatus includes: a two-dimensional (2D) aperture assembly that adjusts an opening area of a via hole through which light is transmitted; a three-dimensional (3D) aperture plate that forms a first opening and a second opening by blocking a part of the via hole, or moving to outside of the via hole to open the via hole; a first shielding plate that is movable to open or close the first opening; and a second shielding plate that is movable so as to close the second opening when the first shielding plate opens the first opening and to open the second opening when the first shielding plate closes the first opening. | 01-31-2013 |
20130027790 | POSITION SENSOR ASSEMBLY AND OPTICAL DEVICE INCLUDING THE SAME - Position sensor assemblies having compact structures and capable of precisely sensing a position change, and optical devices including the same are disclosed. A position sensor assembly is provided that includes: a sensing unit that outputs a signal varying as a magnetic force varies; and a magnet spaced apart from the sensing unit and i movably disposed with respect to the sensing unit, and comprising protrusion units of opposite polarities that protrude from each end portion of the magnet in one surface of the magnet toward the sensing unit. | 01-31-2013 |
Patent application number | Description | Published |
20140079428 | IMAGE FORMING APPARATUS, HOST APPARATUS, SERVER, AND METHOD OF PERFORMING IMAGE FORMING JOB THEREOF - An image forming apparatus includes a storage unit, an interface unit which is connected to a host apparatus and at least one of other image forming apparatuses, an image forming unit which prints image data received through the interface unit, and a controller which, if image data is received when the image forming apparatus is in a normal mode, controls the image forming unit to perform an image forming job using the image data, and if the image data is received when the image forming apparatus is in a power saving mode, controls the interface unit to transmit the image data to another image forming apparatus so that the another image forming apparatus performs an image forming job. | 03-20-2014 |
20150067986 | HINGE ASSEMBLY AND IMAGE FORMING APPARATUS HAVING THE SAME - An image forming apparatus including a hinge assembly to mutually hinge-connect a main body and a cover unit of the image forming apparatus and the hinge assembly is provided. The image forming apparatus includes a main body, a cover unit configured to be disposed on an upper side of the main body to press a manuscript, and at least one hinge assembly configured to connect the cover unit to the main body, wherein the hinge assembly includes a first body detachably mounted on the main body, a second body of which a part is fastened to the cover unit and another part is hinge-connected with the first body, a pressing unit accommodated in the first body to press the second body upward, and a pressing force adjuster configured to adjust a hinge force between the first body and the second body. | 03-12-2015 |
20150365561 | IMAGE FORMING APPARATUS AND METHOD FOR CONTROLLING THE SAME - An image forming apparatus is provided. The image forming apparatus may include an image forming unit to print data, a body portion disposed in the image forming unit, a display unit disposed on the body portion to be spaced apart from the body portion at a predetermined interval, and a scan unit disposed below the display unit, and a scan space is formed between the image forming unit and the display unit. | 12-17-2015 |
Patent application number | Description | Published |
20090251181 | Method and apparatus for tuning phase of clock signal - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 10-08-2009 |
20100008169 | Latency Control Circuit and Method Thereof and an Auto-Precharge Control Circuit and Method Thereof - A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal. | 01-14-2010 |
20110158030 | METHOD AND APPARATUS FOR TUNING PHASE OF CLOCK SIGNAL - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 06-30-2011 |
Patent application number | Description | Published |
20120039564 | Photoelectric Integrated Circuit Devices And Methods Of Forming The Same - A photoelectric integrated circuit device may include a substrate including an electronic device region and an on die optical input/output device region, the substrate having a trench in the on die optical input/output device region; a lower clad layer provided in the trench, the lower clad layer having an upper surface lower than a surface of the substrate; a core provided on the lower clad layer; an insulating pattern provided on the core; an optical detection pattern provided on the insulating pattern, the optical detection pattern having at least a portion provided in the trench; and at least one transistor provided on the substrate of the electronic device region. | 02-16-2012 |
20130127019 | SEMICONDUCTOR DEVICES INCLUDING THROUGH SILICON VIA ELECTRODES AND METHODS OF FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed. | 05-23-2013 |
20130200526 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME - Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode. | 08-08-2013 |
20140035144 | Semiconductor Devices Having Through Electrodes and Methods of Fabricating the Same - Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate. | 02-06-2014 |
20140084473 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer. | 03-27-2014 |
20150137326 | SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer. | 05-21-2015 |
20150287680 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES CAPPED WITH SELF-ALIGNED PROTECTION LAYERS AND METHODS FOR FABRICATING SAME - Semiconductor devices having through electrodes capped with self-aligned protection layers. The semiconductor device comprises a semiconductor substrate including an integrated circuit formed therein, an interlayer dielectric layer on the semiconductor substrate to cover the integrated circuit, an intermetal dielectric layer having at least one metal line that is provided on the interlayer dielectric layer and is electrically connected to integrated circuit, and a through electrode that vertically penetrates the interlayer dielectric layer and the semiconductor substrate. The through electrode includes a top portion that is capped with a first protection layer capable of preventing a constituent of the through electrode from being diffused away from the through electrode. | 10-08-2015 |
20150332967 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer. | 11-19-2015 |
Patent application number | Description | Published |
20100065912 | STACKED SEMICONDUCTOR DEVICE AND RELATED METHOD - A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench. | 03-18-2010 |
20110318922 | METHOD OF FORMING SEMICONDUCTOR DEVICE - The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern. | 12-29-2011 |
20110318923 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME INCLUDING A CONDUCTIVE STRUCTURE IS FORMED THROUGH AT LEAST ONE DIELECTRIC LAYER AFTER FORMING A VIA STRUCTURE - For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized. | 12-29-2011 |
20120043666 | Semiconductor Device and Method of Fabricating the Same - For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized. | 02-23-2012 |
20120132986 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a plurality of horizontal channel transistors formed thereon, an insulation layer structure on the substrate and covering the horizontal transistors, and a plurality of vertical channel transistors on the insulation layer structure. | 05-31-2012 |
20120142185 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring. | 06-07-2012 |
20120282736 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING THE SAME - In a method of manufacturing a semiconductor device, a front end of line (FEOL) process may be performed on a semiconductor substrate to form a semiconductor structure. A back end of line (BEOL) process may be performed on the semiconductor substrate to form a wiring structure electrically connected to the semiconductor structure, thereby formed a semiconductor chip. A hole may be formed through a part of the semiconductor chip. A preliminary plug may have a dimple in the hole. The preliminary plug may be expanded into the dimple by a thermal treatment process to form a plug. Thus, the plug may not have a protrusion protruding from the upper surface of the semiconductor chip, so that the plug may be formed by the single CMP process. | 11-08-2012 |
20130140697 | Electrode Connecting Structures Containing Copper - Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode. | 06-06-2013 |
20130187287 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad. | 07-25-2013 |
20130337647 | METHODS OF FORMING A SEMICONDUCTOR DEVICE - The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern. | 12-19-2013 |
20150028450 | INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE AND DECOUPLING CAPACITOR AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure. | 01-29-2015 |
20150028494 | INTEGRATED CIRCUIT DEVICE HAVING THROUGH-SILICON-VIA STRUCTURE AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT DEVICE - Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via insulating film substantially surrounding the TSV structure, and an insulating spacer disposed between the interlayer insulating film and the via insulating film. | 01-29-2015 |
20150102497 | Integrated Circuit Devices Including a Through-Silicon Via Structure and Methods of Fabricating the Same - Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad. | 04-16-2015 |
20150108605 | Integrated Circuit Devices Having Through Silicon Via Structures and Methods of Manufacturing the Same - An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad. | 04-23-2015 |
Patent application number | Description | Published |
20120113030 | APPARATUS AND METHOD FOR CONTROLLING TERMINAL - An apparatus and method for controlling a terminal is provided. A terminal control apparatus may set a virtual display space in an outer circumferential portion of the terminal and map at least one file to the virtual display space. Through this, a display region of the terminal may be expanded to an outer circumferential region of the terminal. | 05-10-2012 |
20120169740 | IMAGING DEVICE AND COMPUTER READING AND RECORDING MEDIUM - Provided are a display device and a non-transitory computer-readable recording medium. By comparing a priority of an animation clip corresponding to a predetermined part of an avatar of a virtual world with a priority of motion data and by determining data corresponding to the predetermined part of the avatar, a motion of the avatar in which motion data sensing a motion of a user of a real world is associated with the animation clip may be generated. | 07-05-2012 |
20120188237 | VIRTUAL WORLD PROCESSING DEVICE AND METHOD - A virtual world processing apparatus and method. Sensed information, which is information collected by a sensor is inputted. The sensed information is adapted, based on a sensor capability, which is information on capability of the sensor. Accordingly, interoperability between a real world and a virtual world or interoperability between virtual worlds may be achieved. | 07-26-2012 |
20120191737 | VIRTUAL WORLD PROCESSING DEVICE AND METHOD - Disclosed are a virtual world processing device and method. By way of example, data collected from the real world is converted to binary form data which is then transmitted, or is converted to XML data, or the converted XML data is further converted to binary form data which is then transmitted, thereby allowing the data transmission rate to be increased and a low bandwidth to be used, and, in the case of a data-receiving adaptation RV engine, the complexity of the adaptation RV engine can be reduced as there is no need to include an XML parser. | 07-26-2012 |
20130088424 | DEVICE AND METHOD FOR PROCESSING VIRTUAL WORLDS - A device and method for processing virtual worlds. According to embodiments of the present disclosure, information which is measured from the real world using characteristics of a sensor is transferred to a virtual world, to thereby implement an interaction between the real world and the virtual world. The disclosed device and method for processing virtual worlds involve selectively transferring information, from among the measured information, which is different from previously measured information. The disclosed device and method for processing virtual worlds involve transferring the entire measured information in the event that the measured information is significantly different from the previously measured information and for selectively transferring information, from among the measured information, which is different from the measured information in the event that the difference is not significant. | 04-11-2013 |
20130103703 | SYSTEM AND METHOD FOR PROCESSING SENSORY EFFECTS - A system and method for processing sensory effects. According to an embodiment of the present disclosure, sensory effects included in content may be implemented in the real world by generating command data for controlling a sensory device based on sensory effect information and specific information about the sensory device. In addition, the data transmission rate is high and a low bandwidth may be used by encoding metadata as binary before transmission, or encoding as XML before transmission, or encoding as XML and then further encoding as binary before transmission. | 04-25-2013 |
20150065878 | METHODS AND APPARATUSES FOR MONITORING TEMPERATURE CHANGE OF REGION OF INTEREST BY USING PERIODIC BIO-SIGNALS OF OBJECT - A method of generating an image by using ultrasound waves. The method includes acquiring a first bio-signal of an object, generating at least one first ultrasound frame by using at least one echo signal obtained from at least one first ultrasound wave transmitted to a preset region of interest (ROI) of the object, generating a second ultrasound frame by using an echo signal obtained from a second ultrasound wave transmitted to the preset ROI, and acquiring a second bio-signal of the object at a time when the second ultrasound wave is transmitted to be used for generating the second ultrasound frame, and determining a reference frame from among the generated at least one first ultrasound frame based on the generated second ultrasound frame and the acquired second bio-signal. | 03-05-2015 |
20160030851 | VIRTUAL WORLD PROCESSING DEVICE AND METHOD - Disclosed are a virtual world processing device and method. By way of example, data collected from the real world is converted to binary form data which is then transmitted, or is converted to XML data, or the converted XML data is further converted to binary form data which is then transmitted, thereby allowing the data transmission rate to be increased and a low bandwidth to be used, and, in the case of a data-receiving adaptation RV engine, the complexity of the adaptation RV engine can be reduced as there is no need to include an XML parser. | 02-04-2016 |