Patent application number | Description | Published |
20100118203 | Method and device for estimating video noise - A method for estimating noise in a series of video frames includes selecting a region of a first frame, calculating high frequency quantities for the selected region, calculating temporal-domain high frequency quantities for the selected region of the frame and a mapping region of a second frame, and generating a noise estimate of the noise according to a relationship between the high frequency quantities and the temporal-domain high frequency quantities. | 05-13-2010 |
20120176471 | Systems and Methods for Performing Video Conversion Based on Non-Linear Stretch Information - A method implemented in a computing system for converting two-dimensional (2D) video to three-dimensional (3D) format comprises sampling the 2D video, wherein the sampling is performed non-linearly in one or more directions. The method further comprises determining depth information of one or more objects within the 2D video based on sampling information and transforming the 2D video to a 3D-compatible format according to the sampling and the depth information. | 07-12-2012 |
20130202221 | SYSTEMS AND METHODS FOR MODIFYING STEREOSCOPIC IMAGES - Various embodiments are disclosed for modifying stereoscopic images. One embodiment is a method implemented in an image processing device for modifying stereoscopic images. The method comprises retrieving, by an image processing device, a stereoscopic image having at least a first view image and a second view image and retrieving an orientation selection relating to the stereoscopic image, the orientation selection comprising a selection other than one of: a horizontal flip selection and a 180 degree rotation selection. The method further comprises calculating a depth map according to at least part of the stereoscopic image, rotating the first view image based on the orientation selection to obtain a rotated first view image, and generating a new second view image according to the depth map and the rotated first view image. | 08-08-2013 |
20130336577 | Two-Dimensional to Stereoscopic Conversion Systems and Methods - In one embodiment, a two-dimensional to stereoscopic conversion method, comprising: estimating a local motion region in a first image relative to one or more second images, the first and the one or more second images comprising two-dimensional images; generating a color model based on the local motion region; calculating a similarity value for each of at least one image pixel selected from the first image based on the color model; and assigning a depth value for each of the at least one image pixel selected from the first image based on the calculated similarity value to generate a stereoscopic image, the method performed by one or more processors. | 12-19-2013 |
20140254930 | Systems and Methods for Performing Edge Enhancement in Digital Images - A system for editing a digital image comprises a low pass filter for receiving a source image and for filtering high spatial frequency components of the source image to generate a smoothed image. An arithmetic operator unit subtracts color values of the smoothed image from color values of the source image to produce a first image value on pixel-by-pixel basis. A gradient reversal analyzer compares gradient values of the smoothed image to gradient values of the source image and generates a control signal. A boost controller generates a new value for each pixel of a boost parameter map according to the control signal. The boost controller applies the boost parameter map to modify the first image value to generate a second image value. The arithmetic operator unit is further configured to generate an edge enhanced image according to color values of the source image and the second image value. | 09-11-2014 |
Patent application number | Description | Published |
20150021710 | Methods for Forming STI Regions in Integrated Circuits - A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface. | 01-22-2015 |
20150060959 | Eliminating Fin Mismatch Using Isolation Last - An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI) region, an isolation fin spaced apart from the outer fin by the STI region, the isolation fin including a body portion, an isolation oxide, and an etch stop layer, the etch stop layer interposed between the body portion and the isolation oxide and between the STI region and the isolation oxide, and a gate formed over the inner fin, the outer fin, and the isolation fin. | 03-05-2015 |
Patent application number | Description | Published |
20100136791 | Method of Reducing Delamination in the Fabrication of Small-Pitch Devices - A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer. | 06-03-2010 |
20120028473 | Method of Reducing Delamination in the Fabrication of Small-Pitch Devices - A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer. | 02-02-2012 |
20130040446 | Backside Surface Treatment of Semiconductor Chips - A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O | 02-14-2013 |
20130113061 | IMAGE SENSOR TRENCH ISOLATION WITH CONFORMAL DOPING - Provided is a semiconductor image sensor device. The image sensor device includes a substrate. The image sensor device includes a first pixel and a second pixel disposed in the substrate. The first and second pixels are neighboring pixels. The image sensor device includes an isolation structure disposed in the substrate and between the first and second pixels. The image sensor device includes a doped isolation device disposed in the substrate and between the first and second pixels. The doped isolation device surrounds the isolation structure in a conformal manner. | 05-09-2013 |
20130285130 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH NEGATIVELY CHARGED LAYER - A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these. | 10-31-2013 |
20130329102 | IMAGE SENSOR HAVING COMPRESSIVE LAYERS - An image sensor device including a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon oxide, and is negatively charged. The second compressively-stressed layer contains silicon nitride, and is negatively charged. A metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a third compressively-stressed layer formed on the metal shield and the second compressively-stressed layer. The third compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the third compressively-stressed layer. | 12-12-2013 |
20150028402 | PHOTODIODE GATE DIELECTRIC PROTECTION LAYER - The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor. | 01-29-2015 |
20150056739 | IMAGE SENSOR TRENCH ISOLATION WITH CONFORMAL DOPING - Provided is a semiconductor image sensor device. The image sensor device includes a substrate. The image sensor device includes a first pixel and a second pixel disposed in the substrate. The first and second pixels are neighboring pixels. The image sensor device includes an isolation structure disposed in the substrate and between the first and second pixels. The image sensor device includes a doped isolation device disposed in the substrate and between the first and second pixels. The doped isolation device surrounds the isolation structure in a conformal manner. | 02-26-2015 |
20150060964 | MECHANISMS FOR FORMING IMAGE SENSOR DEVICE - Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and one photodetector formed in the semiconductor substrate. The image sensor device also includes one gate stack formed over the semiconductor substrate. The gate stack includes multiple polysilicon layers. | 03-05-2015 |
20150255400 | Method for Forming Alignment Marks and Structure of Same - A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks. | 09-10-2015 |
20150263055 | SEMICONDUCTOR DEVICE WITH COMPRESSIVE LAYERS - A semiconductor device includes a substrate having a first side and a second side opposite the first side. The substrate has a sensor region proximate the first side. The semiconductor device also includes a first compressive layer over the second side of the substrate. The semiconductor device further includes a light blocking element over the first compressive layer. The semiconductor device additionally includes a second compressive layer over the first compressive layer and covering a portion of the light blocking element. The semiconductor device also includes a third compressive layer between the second compressive layer and the portion of the light blocking element. | 09-17-2015 |
20150372034 | HIGH DIELECTRIC CONSTANT STRUCTURE FOR THE VERTICAL TRANSFER GATES OF A COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) IMAGE SENSOR - A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided. | 12-24-2015 |
20150380447 | DEEP TRENCH ISOLATION SHRINKAGE METHOD FOR ENHANCED DEVICE PERFORMANCE - Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device. | 12-31-2015 |
Patent application number | Description | Published |
20130188433 | MEMORY CIRCUIT AND METHOD OF WRITING DATUM TO MEMORY CIRCUIT - A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node. | 07-25-2013 |
20140119101 | WORDLINE TRACKING FOR BOOSTED-WORDLINE TIMING SCHEME - Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal. | 05-01-2014 |
20140211578 | BOOSTED READ WRITE WORD LINE - One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example. | 07-31-2014 |
20150130068 | APPARATUS AND METHOD OF THREE DIMENSIONAL CONDUCTIVE LINES - An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column. | 05-14-2015 |
20150277770 | MEMORY DEVICE WITH TRACKING MECHANISM - A memory device includes storage layers each comprising memory cells arranged in a plurality of rows, bit lines coupled to the memory cells in the corresponding rows, tracking cells arranged in at least one row, at least one tracking bit line coupled to the tracking cells, and at least one sense amplifier coupled to the bit lines. The sense amplifier is configured to detect data stored in the memory cells, and has an enabling terminal coupled to the at least one tracking bit line. The memory device further comprises word lines and tracking word lines extending through the storage layers. The word lines are coupled to the corresponding memory cells in the storage layers. The tracking word lines are coupled to the corresponding tracking cells in the storage layers. | 10-01-2015 |
20150348598 | STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME - A static random access memory (SRAM) that includes a memory cell comprising at least two p-type pass gates. The SRAM also includes a first data line connected to the memory cell, a second data line connected to the memory cell and a voltage control unit connected to the first data line, wherein the voltage control unit is configured to control the memory cell. | 12-03-2015 |
20150380082 | BOOSTED READ WRITE WORD LINE - One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example. | 12-31-2015 |
20160111143 | STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME - A static random access memory (SRAM) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory cell array and the second memory cell array, a primary driver circuit connected to the first data line and a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM. | 04-21-2016 |
Patent application number | Description | Published |
20150162206 | METHOD FOR ETCHING TARGET LAYER OF SEMICONDUCTOR DEVICE IN ETCHING APPARATUS - A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element. | 06-11-2015 |
20150179531 | Uniformity in Wafer Patterning using Feedback Control - A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer. | 06-25-2015 |
20150214063 | HARD MASK RESHAPING - One or more systems and methods for reshaping a hard mask are provided. A semiconductor arrangement comprises one or more structures formed from a layer according to a target dimension, such as a width criterion, a length criterion, a spacing criterion, or other design constraints. To form such a structure, a hard mask is formed over the layer. Responsive to a dimension, such as a width, of the hard mask not corresponding to the target dimension, a first hard mask portion is modified to create a modified hard mask comprising a modified first hard mask portion. In some embodiments, the first hard mask portion is trimmed to decrease the dimension or coated with a coating material to increase the dimension. An etch of the layer is performed through the modified hard mask to create an etched layer comprising an etched portion, such as the structure, corresponding to the target dimension. | 07-30-2015 |
20150235877 | TARGET DIMENSION UNIFORMITY FOR SEMICONDUCTOR WAFERS - One or more systems and methods for controlling a target dimension for a wafer are provided. A processing chamber, such as an etching chamber, is configured to etch one or more wafers. In some embodiments, during processing of a first wafer of a set of wafers, the processing chamber is coated with a relatively thicker chamber coating than chamber coatings used for subsequently processed wafers of the set of wafers. The increased chamber coating thickness results in the first wafer having a target dimension that is substantially similar to target dimensions of the subsequently processed wafers. In some embodiments, a post wafer cleaning process is performed, but a pre wafer cleaning process is disabled, between processing a final wafer of a first set of wafers and an initial wafer of a second set of wafers so that the final wafer and the initial wafer have substantially similar target dimensions. | 08-20-2015 |
20150279750 | Uniformity in Wafer Patterning using Feedback Control - A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer. | 10-01-2015 |
Patent application number | Description | Published |
20100165923 | WIRELESS NETWORK - A wireless network is provided. The wireless network includes a predetermined wireless router and a plurality of wireless routers. The predetermined wireless router has gateway functionality for accessing an external network. Each wireless router of the wireless routers has a single transceiver, and the wireless routers include at least a wireless router which communicates with other wireless router(s) in the wireless network for forwarding network packets by using a single fixed channel and at least a wireless router which communicates with other wireless router(s) in the wireless network for forwarding network packets by using a plurality of channels. | 07-01-2010 |
20100195515 | NODE APPARATUS, NODE QUANTITY ADJUSTMENT METHOD, AND TANGIBLE MACHINE-READABLE MEDIUM FOR A SENSOR NETWORK - A node apparatus and an adjusting method of a quantity of nodes for a sensor network and a tangible machine-readable medium thereof are provided. The sensor network comprises a plurality of groups, wherein each group has a plurality of nodes. For each group, one of the nodes is set to be a gate node, and each node within the group transmits at least one data of itself to the corresponded gate node. Each gate node calculates a data aggregation time based on a data length per unit time of received data and a predetermined packet length, so that each gate node is able to adjust the quantity of nodes within the group thereof accordingly. | 08-05-2010 |
20140143240 | INFORMATION SEARCH SERVER AND INFORMATION SEARCH METHOD THEREOF - An information search server and an information search method thereof are provided. The information search server includes a transceiver and a processor. The transceiver receives a search message having an original store phone number of an original store from a user device. The processor performs a data mining procedure, according to the original store phone number, to obtain an original store name and an original store address associated with the original store phone number, a category associated with the original store name, an original store latitude and longitude associated with the original store address, and a recommended store information associated with the category and the original store latitude and longitude, and generates a result message having the recommended store information. The transceiver further transmits the result message to the user device. | 05-22-2014 |
20140350874 | SENSING SYSTEM AND METHOD FOR DETECTING AND GRAPHICALLY DISPLAYING ELECTRICITY USAGE INFORMATION - The present invention is to provide a sensing method applicable to a sensing system including at least one detecting device and a mobile communication device, wherein the detecting device is electrically connected between an electrical appliance and a power supply unit for detecting usage information (e.g., voltage value, current value, power value, etc.) of the electricity transmitted from the power supply unit to the electrical appliance, and the mobile communication device is wirelessly connected to the detecting device and is able to transmit setting data inputted by a user to the detecting device so that, after receiving the setting data, the detecting device is able to periodically transmit the electricity usage information to the mobile communication device, allowing the mobile communication device to convert the electricity usage information into a detecting chart and graphically display the detecting chart on a screen of the mobile communication device. | 11-27-2014 |
Patent application number | Description | Published |
20100039359 | Adjustment circuit for color sequential liquid crystal display and adjustment method thereof - An adjustment circuit for color sequential liquid crystal displays and an adjustment method thereof applied to a color sequential liquid crystal display are disclosed. The color sequential liquid crystal display receives a plurality of driving signals from a light-source driving circuit to generate a plurality of primary color backlights and at least one adjusted-color backlight and also receives one display driving signal. The adjusted-color backlight is generated behind one of three primary color backlights. By means of the adjusted-color backlight, the color and brightness of the frame are adjusted. | 02-18-2010 |
20100039362 | Control IC for color sequential liquid crystal display - A control IC (integrated circuit) for color sequential liquid crystal displays (LCD) is revealed. The control IC includes an interface for receiving a command and at least one display data and a timing generator to generate a scan timing signal, a data timing signal, and a driving timing signal. According to the scan timing signal, a scan driving circuit generates a scan signal that is sent to the color sequential LCD. In accordance with the data timing signal, a data driving circuit receives the display data for generating a data signal sent to the color sequential LCD. According to the driving timing signal, a light-source driving circuit generates a plurality of driving signals sent to the color sequential LCD so as to generate a plurality of color backlights. In accordance with the scan signal, the data signal and the plurality of backlights, the color sequential LCD displays a frame. | 02-18-2010 |
20100039450 | Circuit for Controlling Color Sequential Liquid Crystal Display and Method for Controlling the Same - The present invention provides a circuit for controlling a color sequential liquid crystal display (LCD) and a method for controlling the same. The control circuit comprises a light-source driving circuit, a data driving circuit, and a scan driving circuit. The light-source driving circuit produces a driving signal for controlling the color sequential LCD to produce backlight with different colors. The data driving circuit produces a data signal and includes a plurality of data pulses. The scan driving signal produces a scan signal and includes a plurality of scan pulses corresponding to the plurality of data pulses, respectively. By controlling the pluralities of data pulses and scan pulses and the backlight, the color sequential LCD will display an image. The voltage levels of the pluralities of data pulses and scan pulses change according to different images. Thereby, power consumed by the control circuit can be reduced. In addition, color-mixing problems will be reduced according to the present invention. | 02-18-2010 |