Patent application number | Description | Published |
20120017185 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit. | 01-19-2012 |
20120017187 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
20120017189 | ARCHITECTURAL LEVEL POWER-AWARE OPTIMIZATION AND RISK MITIGATION - Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
20120017196 | SYSTEM, ARCHITECTURE AND MICRO-ARCHITECTURE (SAMA) REPRESENTATION OF AN INTEGRATED CIRCUIT - Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) design by receiving a specification of the custom IC including computer readable code to be executed by the custom IC; generating an abstraction of the IC as a system, processor architecture and micro-architecture (SAMA) representation; providing the SAMA representation to a data model having at least an architecture optimization view, a physical design view, and a software tool view; optimizing the processor architecture by iteratively updating the SAMA representation and the data model to automatically generate a processor architecture uniquely customized to the computer readable code which satisfies one or more constraints; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. The foregoing can be done with no or minimal human involvement. | 01-19-2012 |
20120017198 | APPLICATION DRIVEN POWER GATING - Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
20120095583 | ARCHITECTURE GUIDED OPTIMAL SYSTEM PRECISION DEFINITION ALGORITHM FOR CUSTOM INTEGRATED CIRCUIT - Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 04-19-2012 |
20120096417 | INTEGRATED DATA MODEL BASED FRAMEWORK FOR DRIVING DESIGN CONVERGENCE FROM ARCHITECTURE OPTIMIZATION TO PHYSICAL DESIGN CLOSURE - Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code; receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model; automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model; and synthesizing a computer readable description of the chip specification into the custom integrated circuit for semiconductor fabrication. | 04-19-2012 |
20120096420 | INTELLIGENT ARCHITECTURE CREATOR - Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 04-19-2012 |
20120185809 | ARCHITECTURE OPTIMIZER - Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 07-19-2012 |
20120185820 | TOOL GENERATOR - Systems and methods are disclosed to automatically generate software development tools for an automatically generated processor architecture by: receiving a description of a target processor; automatically generating a target compiler using a compiler generator; automatically generating a target assembler using an assembler generator; automatically generating a target linker using a linker generator; automatically generating a target simulator using a simulator generator; automatically generating a target profiler using a profiler generator; iteratively generating a new processor architecture by changing one or more parameters of the processor architecture until all user constraints or requirements are met using the generated target compiler, assembler, linker, simulator, and profiler; for each new processor architecture regenerating the target compiler, assembler, linker, simulator, profiler for the new processor architecture; and synthesizing an optimal generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 07-19-2012 |
20130104097 | PROGRAMMATIC AUTO-CONVERGENT METHOD FOR "PHYSICAL LAYOUT POWER HOT-SPOT" RISK AWARE ASIP ARCHITECTURE CUSTOMIZATION FOR PERFORMANCE OPTIMIZATION - Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 04-25-2013 |
20130111426 | PROGRAMMATIC AUTO-CONVERGENT METHOD FOR PHYSICAL DESIGN FLOORPLAN AWARE RE-TARGETABLE TOOL SUITE GENERATION (COMPILER-IN-THE-LOOP) FOR SIMULTANEOUS INSTRUCTION LEVEL (SOFTWARE) POWER OPTIMIZATION AND ARCHITECTURE LEVEL PERFORMANCE OPTIMIZATION FOR ASIP DESIGN | 05-02-2013 |
20130263067 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication. | 10-03-2013 |
20130346926 | Automatic optimal integrated circuit generator from algorithms and specification - Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. | 12-26-2013 |
20140074900 | ARCHITECTURE GUIDED OPTIMAL SYSTEM PRECISION DEFINITION ALGORITHM FOR CUSTOM INTEGRATED CIRCUIT - Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 03-13-2014 |
20140082325 | INTELLIGENT ARCHITECTURE CREATOR - Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 03-20-2014 |
Patent application number | Description | Published |
20110072319 | Parallel Processing of ETL Jobs Involving Extensible Markup Language Documents - Techniques for running an Extract Transform Load (ETL) job in parallel on one or more processors wherein the ETL job comprises use of an extensible markup language (XML) document are provided. The techniques include receiving an XML document input, identifying a node in the XML document at which partitioning of the XML document is to begin, sending partition information to each respective processor, performing a shallow parsing of the XML document in parallel on the one or more processors, wherein each processor performs shallow parsing using the identified partition node until it reaches its identified partition, using the shallow parsing to generate the partition of the input XML document, wherein each processor generates a different partition of the same XML document, and sending each partition in streaming format to an ETL job instance. | 03-24-2011 |
20130117216 | STAR AND SNOWFLAKE SCHEMAS IN EXTRACT, TRANSFORM, LOAD PROCESSES - A computer-implemented method, computer program product and a system for supporting star and snowflake data schemas for use with an Extract, Transform, Load (ETL) process, comprising selecting a data source comprising dimensional data, where the dimensional data comprises at least one source table comprising at least one source column, importing a data model for the dimensional data into a data integration system, analyzing the imported data model to select a star or snowflake target data schema comprising target dimensions and target facts, generating a meta-model representation by mapping at least one source table or source column to each target fact and target dimension, automatically converting the meta-model representation into one or more ETL jobs, and executing the ETL jobs to extract the dimensional data from the data source and loading the dimensional data into the selected target data schema in a target data system. | 05-09-2013 |
20130117217 | STAR AND SNOWFLAKE SCHEMAS IN EXTRACT, TRANSFORM, LOAD PROCESSES - A computer-implemented method, computer program product and a system for supporting star and snowflake data schemas for use with an Extract, Transform, Load (ETL) process, comprising selecting a data source comprising dimensional data, where the dimensional data comprises at least one source table comprising at least one source column, importing a data model for the dimensional data into a data integration system, analyzing the imported data model to select a star or snowflake target data schema comprising target dimensions and target facts, generating a meta-model representation by mapping at least one source table or source column to each target fact and target dimension, automatically converting the meta-model representation into one or more ETL jobs, and executing the ETL jobs to extract the dimensional data from the data source and loading the dimensional data into the selected target data schema in a target data system. | 05-09-2013 |
20130124454 | Slowly Changing Dimension Attributes in Extract, Transform, Load Processes - A computer-implemented method, computer program product and a system for identifying and handling slowly changing dimension (SCD) attributes for use with an Extract, Transform, Load (ETL) process, comprising importing a data model for dimensional data into a data integration system, where the dimensional data comprises a plurality of attributes, identifying via a data discovery analyzer one or more attributes in the data model as SCD attributes, importing the identified SCD attributes into the data integration system, selecting a data source comprising dimensional data, automatically generating an ETL job for the dimensional data utilizing the imported SCD attributes, and executing the automatically generated ETL to extract the dimensional data from the data source and loading the dimensional data into the imported SCD attributes in a target data system. | 05-16-2013 |
Patent application number | Description | Published |
20080281626 | Enabling Interoperability Between Participants in a Network - Interoperability is enabled between participants in a network by determining values associated with a value metric defined for at least a portion of the network. Information flow is directed between two or more of the participants based at least in part on semantic models corresponding to the participants and on the values associated with the value metric. The semantic models may define interactions between the participants and define at least a portion of information produced or consumed by the participants. The determination of the values and the direction of the information flow may be performed multiple times in order to modify the one or more value metrics. The direction of information flow may allow participants to be deleted from the network, may allow participants to be added to the network, or may allow behavior of the participants to be modified. | 11-13-2008 |
20090006049 | SYSTEM FOR ESTIMATING STORAGE REQUIREMENTS FOR A MULTI-DIMENSIONAL CLUSTERING DATA CONFIGURATION - A storage requirements estimating system estimates the storage required for a proposed multidimensional clustering data by modeling wasted space. The amount of wasted space is modeled by calculating the cardinality of the unique value of the clustering key for the proposed configuration. Cardinality may be determined by estimation techniques. Specific values for wasted space and total space may be determined in response to the determined cardinality. Comparison of estimates for different proposed clustering configurations facilitate a selection among proposed multidimensional clustering data configurations. | 01-01-2009 |
20090089306 | Method, System and Article of Manufacture for Improving Execution Efficiency of a Database Workload - Disclosed is a data processing system implemented method, a data processing system and an article of manufacture for improving execution efficiency of a database workload to be executed against a database. The database includes database tables, and the database workload identifies at least one of the database tables. The data processing system includes an identification module for identifying candidate database tables being identifiable in the database workload, the identified candidate database tables being eligible for organization under a clustering schema, a selection module for selecting the identified candidate tables according to whether execution of the database workload is improved if the selected identified candidate table is organized according to the clustering scheme, and an organization module for organizing the clustering schema of the selected organized identified candidate tables prior to the database workload being execution against the database. | 04-02-2009 |
20090204551 | Learning-Based Method for Estimating Costs and Statistics of Complex Operators in Continuous Queries - A learning-based method for estimating costs or statistics of an operator in a continuous query includes a cost estimation model learning procedure and a model applying procedure. The model learning procedure builds a cost estimation model from training data, and the applying procedure uses the model to estimate the cost associated with a given query. The learning procedure uses a feature extractor, a confidence adjustor and a cost estimator. The feature extractor collects relevant training data and obtains feature values. The extracted feature values are associated with costs and used to create the cost estimator. The extracted feature values, the associated costs, the cost estimator, and a user interface are used to create a confidence adjuster. When applying the confidence adjuster and the cost estimator to a continuous stream of data, the feature extractor extracts feature values from the data stream, uses the extracted feature values as input into the confidence adjuster to determine whether or not the cost estimator should be used, and if so, uses the extracted feature values as inputs into the cost estimator to obtain the desired cost values. | 08-13-2009 |
20110191323 | EFFICIENT MULTIPLE TUPLE GENERATION OVER STREAMING XML DATA - Methods and arrangements for extracting tuples from a streaming XML document. A query twig is applied to the XML document stream, tuples are extracted from the XML document stream based on the query twig, and a quantity of extracted tuples is limited via foregoing extraction of duplicate tuples extraction of tuples that do not satisfy query twig criteria. | 08-04-2011 |
20120047179 | SYSTEMS AND METHODS FOR STANDARDIZATION AND DE-DUPLICATION OF ADDRESSES USING TAXONOMY - Systems and associated methods for address standardization and applications related thereto are described. Embodiments exploit a common context in a taxonomy and a given address to detect and correct deviations in the address. Embodiments establish a possible path from a root of the taxonomy to a leaf in the taxonomy that can possibly generate a given address. Given a new address, embodiments use complete addresses, and/or segments or elements thereof, to compute the representations of the elements and find a closest matching leaf in the taxonomy. Embodiments then traverse the path to a root node to detect the agreement and disagreement between the path and the address entry. Taxonomical structured is thus used to detect, segregate and standardize the expected fields. | 02-23-2012 |
20120078929 | Utilizing Metadata Generated During XML Creation to Enable Parallel XML Processing - A method, computer program product, and system for enabling parallel processing of an XML document without pre-parsing, utilizing metadata associated with the XML document and created at the same time as the XML document. The metadata is used to generate partitions of the XML document at the time of parallel processing, without requiring system-intensive pre-parsing. | 03-29-2012 |
20120079364 | Finding Partition Boundaries for Parallel Processing of Markup Language Documents - A method, a computer program product and a system identify partition locations within an extended markup language (XML) document without parsing so as to process portions of said document in parallel. The XML document includes sections required to remain continuous. The document is scanned for continuous sections without parsing, and boundaries of the initial partitions are adjusted to reside outside the continuous sections to determine resulting partitions for the document. The resulting partitions may be processed in parallel to provide the document information for storage. | 03-29-2012 |
20120131481 | Dynamic De-Identification of Data - The present invention relates to a method, computer program product and system for masking sensitive data and, more particularly, to dynamically de-identifying sensitive data from a data source for a target application, including enabling a user to selectively alter an initial de-identification protocol for the sensitive data elements via an interface. | 05-24-2012 |
20120151597 | De-Identification of Data - The present invention relates to a method, computer program product and system for de-identifying data, wherein a de-identification protocol is selectively mapped to a business rule at runtime via an ETL tool. | 06-14-2012 |
20120166460 | Utilizing Metadata Generated During XML Creation to Enable Parallel XML Processing - A method, computer program product, and system for enabling parallel processing of an XML document without pre-parsing, utilizing metadata associated with the XML document and created at the same time as the XML document. The metadata is used to generate partitions of the XML document at the time of parallel processing, without requiring system-intensive pre-parsing. | 06-28-2012 |
20120266254 | De-Identification of Data - The present invention relates to a method, computer program product and system for de-identifying data, wherein a de-identification protocol is selectively mapped to a business rule at runtime via an ETL tool. | 10-18-2012 |
20120266255 | Dynamic De-Identification of Data - The present invention relates to a method, computer program product and system for masking sensitive data and, more particularly, to dynamically de-identifying sensitive data from a data source for a target application, including enabling a user to selectively alter an initial de-identification protocol for the sensitive data elements via an interface. | 10-18-2012 |
20120311589 | SYSTEMS AND METHODS FOR PROCESSING HIERARCHICAL DATA IN A MAP-REDUCE FRAMEWORK - Methods and arrangements for processing hierarchical data in a map-reduce framework. Hierarchical data is accepted, and a map-reduce job is performed on the hierarchical data. This performing of a map-reduce job includes determining a cost of partitioning the data, determining a cost of redefining the job and thereupon selectively performing at least one step taken from the group consisting of: partitioning the data and redefining the job. | 12-06-2012 |
20120324459 | PROCESSING HIERARCHICAL DATA IN A MAP-REDUCE FRAMEWORK - Methods and arrangements for processing hierarchical data in a map-reduce framework. Hierarchical data is accepted, and a map-reduce job is performed on the hierarchical data. This performing of a map-reduce job includes determining a cost of partitioning the data, determining a cost of redefining the job and thereupon selectively performing at least one step taken from the group consisting of: partitioning the data and redefining the job. | 12-20-2012 |
20130086116 | DECLARATIVE SPECIFICATION OF DATA INTEGRATON WORKFLOWS FOR EXECUTION ON PARALLEL PROCESSING PLATFORMS - A method for receiving a declarative specification including a plurality of stages. Each stage specifies an atomic operation, a data input to the atomic operation, and a data output from the atomic operation. The data input is characterized by a data type. Links between at least two of the stages are generated to create a data integration workflow. The data integration workflow is compiled to generate computer code for execution on a parallel processing platform. The computer code configured to perform at least one of data preparation and data analysis. | 04-04-2013 |
20130124453 | SLOWLY CHANGING DIMENSION ATTRIBUTES IN EXTRACT, TRANSFORM, LOAD PROCESSES - A computer-implemented method, computer program product and a system for identifying and handling slowly changing dimension (SCD) attributes for use with an Extract, Transform, Load (ETL) process, comprising importing a data model for dimensional data into a data integration system, where the dimensional data comprises a plurality of attributes, identifying via a data discovery analyzer one or more attributes in the data model as SCD attributes, importing the identified SCD attributes into the data integration system, selecting a data source comprising dimensional data, automatically generating an ETL job for the dimensional data utilizing the imported SCD attributes, and executing the automatically generated ETL to extract the dimensional data from the data source and loading the dimensional data into the imported SCD attributes in a target data system. | 05-16-2013 |
20130254237 | DECLARATIVE SPECIFICATION OF DATA INTEGRATON WORKFLOWS FOR EXECUTION ON PARALLEL PROCESSING PLATFORMS - A method for receiving a declarative specification including a plurality of stages. Each stage specifies an atomic operation, a data input to the atomic operation, and a data output from the atomic operation. The data input is characterized by a data type. Links between at least two of the stages are generated to create a data integration workflow. The data integration workflow is compiled to generate computer code for execution on a parallel processing platform. The computer code configured to perform at least one of data preparation and data analysis. | 09-26-2013 |
20150026115 | CREATION OF CHANGE-BASED DATA INTEGRATION JOBS - A computer software implemented method for transforming a first extract transform load (ETL) job having at least some unload transform load (UTL) portions. The method includes the following steps: (i) decomposing the first ETL job into an intermediate set of one or more jobs; and (ii) for each job of the intermediate set, transforming the job into a transactionally equivalent job to yield a final set of one or more jobs. The decomposing is performed so that each job of the intermediate jobs set is a Simple UTL job. The transforming is performed so that each job of the final set includes no UTL portions. | 01-22-2015 |
20150040133 | MULTIPLE STAGE WORKLOAD MANAGEMENT SYSTEM - Provided are techniques for multiple stage workload management. A staging queue and a run queue are provided. A workload is received. In response to determining that application resources are not available and that the workload has not been previously semi-started, the workload is added to the staging queue. In response to determining that the application resources are not available and that the workload has been semi-started, and, in response to determining that run resources are available, the workload is started. In response to determining that the application resources are not available and that the workload has been semi-started, and, in response to determining that the run resources are not available, adding the workload to the run queue. | 02-05-2015 |
20150095341 | SYSTEM AND A METHOD FOR HIERARCHICAL DATA COLUMN STORAGE AND EFFICIENT QUERY PROCESSING - An embodiment provides intermediate data derived in the form of column stores which are in turn based on hierarchical data stores. This intermediate data represents a reduced subset of data matched appropriately to a query (or modified query) such that the amount of data handled in a query processing task on large data is greatly reduced. An embodiment may appropriately choose column data stores and/or modify queries in order leverage parallelization techniques such as map-reduce in order to query large data. The result is the ability to query large data stores in parallel while reducing the amount of data that must be handled. | 04-02-2015 |
20150242477 | ETL JOB CREATION USING BUSINESS TERM STAGE - A computer determines a business glossary, wherein the business glossary includes one or more business terms that correspond to one or more assets. The computer receives a request to create an ETL job associated with a business term. The computer creates an ETL job for the business term, wherein the ETL job includes a business glossary stage. | 08-27-2015 |
20150262185 | CONFIDENTIAL FRAUD DETECTION SYSTEM AND METHOD - Various embodiments for maintaining security and confidentiality of data and operations within a fraud detection system. Each of these embodiments utilizes a secure architecture in which: (1) access to data is limited to only approved or authorized entities; (2) confidential details in received data can be readily identified and concealed; and (3) confidential details that have become non-confidential can be identified and exposed. | 09-17-2015 |
Patent application number | Description | Published |
20100128660 | EFFICIENT CONTROL SIGNALING OVER SHARED COMMUNICATION CHANNELS WITH WIDE DYNAMIC RANGE - Embodiments provide methods, apparatuses, and systems for efficient control signaling over shared communication channels with wide dynamic range. Some embodiments includes a gateway configured to encode and to transmit multiple physical layer headers, including a first physical layer header and a second physical layer header. The first physical layer header may span a first length and represent a first modcode; the second physical layer header may span a second length and represent a second modcode. The second length may be longer than the first length. Embodiments may include multiple terminals in wireless communication with the gateway via satellite, including a first terminal configured to decode the first physical layer header and to determine the first modcode. Embodiments may include a second terminal configured to decode the second physical layer header and determine the second modcode. | 05-27-2010 |
20100128661 | MOBILE SATELLITE COMMUNICATION - Embodiments provide methods, systems, and apparatuses for adaptive coding, sampling, and modulating over a satellite communication channel. In some embodiments, a method of adaptive coding, sampling, and modulating over a satellite communication channel may include providing multiple data frames. At least one modcode partition may be provided for each data frame. The modcode partitions may represent modulation, coding, spreading, and/or frame size information for respective data frames. Each data frame and the respective modcode partition may be combined to form a modcode data unit. Multiple superframes may be formed. Each superframe may include a first known sequence and multiple subframes. Each subframe for a respective superframe may include a portion of a respective modcode data unit. Multiple superframes may be transmitted across a wireless channel. | 05-27-2010 |
20120287846 | EFFICIENT CONTROL SIGNALING OVER SHARED COMMUNICATION CHANNELS WITH WIDE DYNAMIC RANGE - Embodiments provide methods, apparatuses, and systems for efficient control signaling over shared communication channels with wide dynamic range. Some embodiments includes a gateway configured to encode and to transmit multiple physical layer headers, including a first physical layer header and a second physical layer header. The first physical layer header may span a first length and represent a first modcode; the second physical layer header may span a second length and represent a second modcode. The second length may be longer than the first length. Embodiments may include multiple terminals in wireless communication with the gateway via satellite, including a first terminal configured to decode the first physical layer header and to determine the first modcode. Embodiments may include a second terminal configured to decode the second physical layer header and determine the second modcode. | 11-15-2012 |
20130223320 | EFFICIENT CONTROL SIGNALING OVER SHARED COMMUNICATION CHANNELS WITH WIDE DYNAMIC RANGE - Embodiments provide methods, apparatuses, and systems for efficient control signaling over shared communication channels with wide dynamic range. Some embodiments includes a gateway configured to encode and to transmit multiple physical layer headers, including a first physical layer header and a second physical layer header. The first physical layer header may span a first length and represent a first modcode; the second physical layer header may span a second length and represent a second modcode. The second length may be longer than the first length. Embodiments may include multiple terminals in wireless communication with the gateway via satellite, including a first terminal configured to decode the first physical layer header and to determine the first modcode. Embodiments may include a second terminal configured to decode the second physical layer header and determine the second modcode. | 08-29-2013 |