Patent application number | Description | Published |
20100117194 | METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE - A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed. | 05-13-2010 |
20100187655 | Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers. | 07-29-2010 |
20110278698 | Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers. | 11-17-2011 |
20130130465 | METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers. | 05-23-2013 |
Patent application number | Description | Published |
20100178922 | Apparatus and method for handover in mobile communication system - An apparatus and method for handover in a mobile communication system enables a Mobile Station (MS) to perform a normal handover without performing an unnecessary handover. A Base Station (BS) apparatus capable of preventing an unnecessary handover includes a handover manager. The handover manager receives handover information, including information about at least one cell through which an MS has passed, from a neighbor cell to determine whether the MS has performed an unnecessary handover. If it is determined that the MS has performed an unnecessary handover, the handover manager notifies the occurrence of the unnecessary handover by the MS to the neighbor cell. | 07-15-2010 |
20100234027 | METHOD AND SYSTEM FOR IMPROVING CALL DROP CAUSED BY RADIO LINK FAILURE IN MOBILE COMMUNICATION SYSTEM - A method and system for improving a call drop caused by a Radio Link Failure (RLF) before handover triggering in a mobile communication system are provided. The method of improving the call drop caused by the RLF in the mobile communication system includes detecting an RLF occurring before handover triggering (RLF_before_HO), generating one of an RLF_before_HO-dependent statistics and an RLF_before_HO-dependent log file, transmitting the one of the RLF_before_HO-dependent statistics and the RLF_before_HO-dependent log file to a serving Base Station (BS), and updating a Neighbor Relation Table (NRT) and optimizing a handover parameter using the one of the RLF_before_HO-dependent statistics and the RLF_before_HO-dependent log file. | 09-16-2010 |
20100234039 | COMMUNICATION SYSTEM WITH FEMTOCELLS AND AN INTERFERENCE CONTROL METHOD THEREFOR - A wireless communication system with femtocells and a method for mitigating inter-cell interference in the wireless communication system are provided. The interference control method includes notifying a mobile station of entry to a home cell, when the mobile station enters a macrocell including a femto base station with which the mobile station is registered, transmitting, by the mobile station, a femtocell driving control message to the femto base station at a predetermined transmission power, when the mobile station enters a femtocell of the femto base station, and switching on, by the femto base station, a transmitter, when the femtocell driving control message is received. | 09-16-2010 |
20110028181 | APPARATUS AND METHOD FOR CONFIGURATION AND OPTIMIZATION OF AUTOMATIC NEIGHBOR RELATION IN WIRELESS COMMUNICATION SYSTEM - An apparatus and method for configuration and optimization of an Automatic Neighbor Relation (ANR) in a wireless communication system are provided. The method of configuring the ANR by a Base Station (BS) in the wireless communication system includes receiving a measurement report message for reporting a neighbor cell's signal quality from one or more User Equipments (UEs), determining a neighbor cell, reported from a UE in an area where a serving cell's signal quality is greater than a first reference value, as an Overlay Neighbor (ON), among neighbor cells reported using the measurement report message, and determining a neighbor cell, reported from a UE in an area where the serving cell's signal quality is less than a second reference value, as a Horizontal Neighbor (HN), among the neighbor cells reported using the measurement report message, wherein the second reference value is set to a value smaller than the first reference value. | 02-03-2011 |
20110044285 | Apparatus and method for handover optimization in broadband wireless communication system - A method and apparatus optimize handover optimization in a broadband wireless communication system. Operations of a base station includes determining whether at least one of a plurality of time intervals included in a total time taken by handover, exceeds a threshold time. Whether to advance or delay a handover point is determined based on which at least one of the time interval exceeds the threshold time. And at least one handover parameter is changed to advance or delay the handover point. | 02-24-2011 |
20110124312 | SYSTEM AND METHOD FOR PERFORMING EMERGENCY CALL IN WIRELESS COMMUNICATION NETWORK, AND BASE STATION - A system and method for performing an emergency call is disclosed that can reduce inter-cell interference. A wireless communication system for performing an emergency call includes an emergency call mobile station for requesting the emergency call; a relay mobile station for relaying the emergency call request to a serving base station; a serving base station for receiving the emergency call request via the relay mobile station, determining an emergency call transmission resource, and requesting its ambient base stations so as not to use the determined emergency call transmission resource; and ambient base stations for preventing the use of the area of the transmission resource, to which the emergency call transmission resource is allocated. | 05-26-2011 |
20150104623 | PATTERNING METHOD FOR GRAPHENE USING HOT-EMBOSSING IMPRINTING - The present application provides a patterning method of a graphene, including a step of forming a graphene layer on a polymer substrate and a step of forming a nanopattern on the graphene layer by hot embossing imprinting. | 04-16-2015 |
20150259800 | PREPARING METHOD OF GRAPHENE BY USING NEAR-INFRARED AND APPARATUS THEREFOR - The present disclosures described herein pertain generally to a method and an apparatus for preparing a graphene by using near-infrared light. | 09-17-2015 |
Patent application number | Description | Published |
20130286624 | DISPLAY DEVICE - A display device includes a display panel having a display area and a bezel area formed around edges of the display area; a backlight unit disposed on a rear side of the display panel to provide light to the display panel; a supporting member to support the display panel and the backlight unit; and a top case having at least one joint and incorporated with a surface of the supporting member, wherein the top case has a main frame combined with the supporting member, and a sub frame having a design of at least one color and disposed on the bezel area. | 10-31-2013 |
20130286627 | DISPLAY DEVICE - A display device includes a display panel having a display area and a bezel area formed around edges of the display area; a backlight unit disposed on a rear side of the display panel to provide light to the display panel; a supporting member to support the display panel and the backlight unit; and a top case having at least one joint and incorporated with a surface of the supporting member, wherein the top case has a main frame combined with the supporting member and a sub frame disposed on the bezel area and combined with the main frame. | 10-31-2013 |
20150370353 | Optical Touch Display Device and Driving Method Thereof - An optical touch display device which is advantageous in high-speed driving, large-area touch sensing, and multi-touch sensing because of use of an image map and which can improve touch sensing performance and a driving method thereof are provided. The optical touch display device includes a display device configured to display a display image based on input source image data and an image map for touch sensing, an optical touch pen configured to detect map information of the image map displayed on the display device, and a position detector configured to detect position information (coordinate information) on a screen based on the map information. | 12-24-2015 |
Patent application number | Description | Published |
20090040929 | Method and apparatus for dynamically managing hierarchical flows - Provided are a method and apparatus for dynamically managing hierarchical flows that more efficiently process packet traffic while maintaining compatibility with an existing packet data network in transferring both circuit traffic and packet traffic in a packet switched network. The method for dynamically managing hierarchical flows includes: receiving data packets, classifying the data packets according to attributes of the received data packets, and producing first flows; determining whether traffic of each of the first flows exceeds a predetermined bandwidth limit, and performing a packet drop process or producing second flows for first flows that exceed the bandwidth limit, according to a flow-specific policy; and performing second flow processing on the second flows according to a second flow policy. Only flows exceeding the bandwidth limit or causing congestion are hierarchically divided for management. This makes it possible to finely manage the flows without complex operations. | 02-12-2009 |
20090086764 | System and method for time synchronization on network - A system and method for time synchronization on a network is provided. According to the system and method for time synchronization, a slave clock device does not continuously receive a time synchronization message periodically transferred from a master clock device and thus does not correct its time upon all such occasions. Rather, the slave clock device requests time information from the master clock device only when the slave clock device needs to correct its time, and receives a time synchronization message transferred from the master clock device and compensates for its time deviation only while the slave clock device is activated, thereby reducing its power consumption and amount of computation. | 04-02-2009 |
20100158009 | HIERARCHICAL PACKET PROCESS APPARATUS AND METHOD - Provided is a hierarchical packet processing apparatus and method. In one general aspect, a packet is analyzed, divided into an upper layer and a lower layer. It is determined whether a property of the packet to be analyzed has been already analyzed or has to be re-analyzed with respect to each of the upper and lower layers of the packet. Therefore, deep packet inspection is performed only when it is required, and thus assurance of quality of service (QoS) during packet processing can be achieved, as well as reduced waste of resources. | 06-24-2010 |
20110013737 | TIME SYNCHRONIZATION APPARATUS BASED ON PARALLEL PROCESSING - A parallel processing-based time synchronization apparatus is disclosed. The time synchronization apparatus employs a double-filter structure based on parallel processing, thereby providing more precise and reliable time synchronization between a master device and a slave device. | 01-20-2011 |
20110051730 | MULTI-LAYER DATA PROCESSING APPARATUS AND METHOD THEREOF - A multi-layer data processing apparatus and method. The multi-layer data processing unit may classify received multi-layer data into lower layer data and higher layer data using lower layer information, and generate and output a traffic flow of the lower layer data or traffic flows of the lower layer data and the higher layer data with reference to a rule information table. In the rule information table, pieces of lower layer rule information may be linked to pieces of higher layer rule information. | 03-03-2011 |
20110107059 | MULTILAYER PARALLEL PROCESSING APPARATUS AND METHOD - A multilayer parallel processing apparatus. The multilayer parallel processing apparatus includes two or more hierarchical parallel processing units, each configured to process flow data corresponding to a hierarchy that is allocated thereto in response to inputting pieces of flow data configured with two or more hierarchies, and a common database configured to be accessed by the two or more hierarchical parallel processing units and store processing results of each of the hierarchical parallel processing units. | 05-05-2011 |
20120124212 | APPARATUS AND METHOD FOR PROCESSING MULTI-LAYER DATA - A multi-layer data processing apparatus and method are provided. The multi-layer data processing apparatus includes a lower hierarchy processing unit configured to generate at least one lower hierarchy flow from input data using lower hierarchy information, and to allocate the generated lower hierarchy flows to a plurality of lower hierarchy processors to perform lower hierarchy processing in respect of the lower hierarchy flows in parallel; and a higher hierarchy processing unit configured to generate at least one higher hierarchy flow from data transmitted from the lower hierarchy processing unit using higher hierarchy information, and to allocate the generated higher hierarchy flows to a plurality of higher hierarchy processors to perform higher hierarchy processing in parallel in respect of the higher hierarchy flows. | 05-17-2012 |
20120155497 | APPARATUS AND METHOD FOR ESTIMATING TIME STAMP - An apparatus includes a difference extraction unit to extract a difference between a second time stamp value, which is obtained by adjusting a first time stamp value that is measured at a time of arrival of a synchronization message transmitted by the master at a Layer 3 to be synchronized in frequency with a clock of the master, and a third time stamp value, which is measured at a time of departure of the synchronization message from the master; a minimum filter to select a minimum from one or more difference values extracted by the difference extraction unit; and a delay variation calculation unit to estimate a time of arrival of a current synchronization message at the Layer 3 based on the selected minimum and calculate a delay variation. | 06-21-2012 |
20140160931 | APPARATUS AND METHOD FOR MANAGING FLOW IN SERVER VIRTUALIZATION ENVIRONMENT, AND METHOD FOR APPLYING QOS - An apparatus and method for managing a flow in a server virtualization environment, and a method of applying a QoS policy, the method including a flow processing unit configured to analyze a flow generated by a virtual machine (VM) to extract flow information, determine whether the flow is a new flow by comparing the extracted flow information with preset flow information, and apply a corresponding Quality of Service (QoS) policy to the flow, and a QoS management unit configured to, in a case in which the flow is a new flow, generate a QoS policy for the analyzed flow based on the extracted flow information and prestored virtual machine information, and transmit the generated QoS policy to the flow processing unit. | 06-12-2014 |
Patent application number | Description | Published |
20100305041 | CELL PERMEABLE P18 RECOMBINANT PROTEINS, POLYNUCLEOTIDES ENCODING THE SAME, AND ANTICANCER COMPOSITION COMPRISING THE SAME - The present invention discloses cell permeable p18 recombinant proteins where a macromolecule transduction domain (MTD) is fused to a tumor suppressor p18. Also disclosed are polynucleotides encoding the cell permeable p18 recombinant proteins, an expression vector containing the cell permeable p18 recombinant protein, and a pharmaceutical composition for treating p18 deficiency or failure which contains the cell permeable p18 recombinant protein as an effective ingredient. The cell permeable p18 recombinant proteins of the present invention are capable of efficiently introducing a haploinsufficient tumor suppressor p18 into a cell, and thus, can activate cell signaling mechanisms involved in the activation of ATM and p53 that induce cell cycle arrest and apoptosis in response to DNA damage or oncogenic signals. Therefore, the cell permeable p18 recombinant proteins of the present invention can be effectively used as an anticancer agent. | 12-02-2010 |
20110021442 | CELL PREAMBLE RUNX3 RECOMBINANT PROTEINS, POLYNUCLEOTIDES ENCODING THE SAME, AND ANTICANCER COMPOSITIONS INCLUDING THE SAME - The present invention discloses cell permeable RUNX3 recombinant proteins where a Macromolecule Transduction Domain (MTD) is fused to a tumor and metastasis suppressor RUNX3. Also disclosed are polynucleotides encoding the cell permeable RUNX3 recombinant proteins, an expression vector containing the cell permeable RUNX3 recombinant protein, and a pharmaceutical composition for preventing metastasis which contains the cell permeable RUNX3 recombinant protein as an effective ingredient. The cell permeable RUNX3 recombinant proteins of the present invention can induce the reactivation of TGF-β signal transduction pathway which causes cell cycle arrest by efficiently introducing a tumor and metastasis suppressor RUNX3 into a cell. Therefore, the cell permeable RUNX3 recombinant proteins of the present invention can be effectively used as an anticancer agent capable of preventing cancer growth and metastasis by suppressing the proliferation, differentiation, and migration of cancer cells. | 01-27-2011 |
20120095188 | ESTABLISHMENT OF INDUCED PLURIPOTENT STEM CELL USING CELL-PERMEABLE REPROGRAMMING TRANSCRIPTION FACTOR FOR CUSTOMIZED STEM CELL THERAPY - The present invention relates to a reprogramming transcription factor recombinant protein in which a macromolecule transduction domain (MTD) is fused to a reprogramming transcription factor to obtain cell permeability. The present invention also relates to a polynucleotide for coding said reprogramming transcription factor recombinant protein and to an expression vector of said cell-permeable reprogramming transcription factor recombinant protein. Treating a somatic cell with the cell-permeable reprogramming transcription factor recombinant protein induces the reprogramming of the stem cell-specific gene of the somatic cell, and thus can be effectively used in the establishment of an induced pluripotent stem cell (iPS cell) having characteristics similar to those of an embryonic stem cell in terms of morphology and genetics. | 04-19-2012 |
Patent application number | Description | Published |
20110306202 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure. | 12-15-2011 |
20120108056 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure. | 05-03-2012 |
20120115322 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure. | 05-10-2012 |
20120276745 | METHOD FOR FABRICATING HOLE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a hole pattern in a semiconductor device includes forming a first organic layer over an etch layer, forming a first inorganic layer pattern over the first organic layer, etching the first organic layer using the first inorganic layer pattern as an etching barrier, forming a second organic layer over the first organic layer, forming a second inorganic layer pattern over the second organic layer, where the second inorganic layer pattern crosses the first inorganic pattern, etching the first and second organic layers using the second inorganic layer pattern as an etching barrier, and etching the etch layer using the etched first and second organic layers as an etch barrier to form a hole pattern. | 11-01-2012 |
20130011987 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL GATE - A method for fabricating a semiconductor device includes forming a plurality of pillars by etching a semiconductor substrate, forming a conductive layer over a semiconductor substrate structure including the pillars, forming preliminary gates on sidewalls of each pillar by performing a first etch process on the conductive layer, and forming vertical gates by performing a second etch process on upper portions of the preliminary gates. | 01-10-2013 |