Patent application number | Description | Published |
20150017571 | PHOTOLITHOGRPAHY SCATTERING BAR STRUCTURE AND METHOD - Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process. | 01-15-2015 |
20150040081 | Method and Apparatus for Integrated Circuit Mask Patterning - Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process. | 02-05-2015 |
20150082265 | DESIGN STRUCTURE FOR CHIP EXTENSION - One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields. | 03-19-2015 |
20150106771 | METHOD OF LITHOGRAPHIC PROCESS EVALUATION - Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model. | 04-16-2015 |
20160085906 | Method and Apparatus for Integrated Circuit Mask Patterning - Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process. | 03-24-2016 |
Patent application number | Description | Published |
20140091462 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods. | 04-03-2014 |
20150102484 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging. | 04-16-2015 |
20150155250 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility. | 06-04-2015 |
20150287671 | PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes. | 10-08-2015 |
20150333029 | PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A package substrate and a method of fabricating the same are provided. The method includes providing a substrate body having a first surface, a second surface opposing the first surface, a plurality of first electrical connecting pads disposed on the first surface; mounting a metal board on the first electrical connecting pads; and patterning the metal board so as to define a plurality of metal pillars corresponding to the first electrical connecting pads. Therefore, drawbacks of raw edges and unequal heights of the metal pillars can be obviated. | 11-19-2015 |
20160079151 | PACKAGE STRUCTURE WITH AN EMBEDDED ELECTRONIC COMPONENT AND METHOD OF FABRICATING THE PACKAGE STRUCTURE - The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives. | 03-17-2016 |
20160079170 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced. | 03-17-2016 |
20160081186 | SUBSTRATE STRUCTURE AND METHOD OF FABRICATING THE SAME - The present invention provides a substrate structure and a method of fabricating the substrate substrure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulative protection layer, and remvoing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied. | 03-17-2016 |
20160099204 | PACKAGE SUBSTRATE, PACKAGE STRUCTURE, AND METHODS OF FABRICATING THE SAME - A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate. | 04-07-2016 |
Patent application number | Description | Published |
20110169150 | Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof - A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity. | 07-14-2011 |
20140021636 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 01-23-2014 |
20140346670 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 11-27-2014 |
Patent application number | Description | Published |
20110273951 | MEMORY CIRCUIT AND METHOD FOR CONTROLLING MEMORY CIRCUIT - A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage, and the fourth supply voltage is coupled to a second supply voltage smaller than the first supply voltage. The switch module is coupled to the second node, the third node, the first supply voltage and the second supply voltage. When the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage, and electrically disconnects the third node from the first supply voltage. | 11-10-2011 |
20120008377 | STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY - A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit. | 01-12-2012 |
20120008449 | LOW POWER STATIC RANDOM ACCESS MEMORY - A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices. | 01-12-2012 |
20120044779 | DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY - A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation. | 02-23-2012 |
Patent application number | Description | Published |
20120015503 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate. | 01-19-2012 |
20120094504 | METHODS OF FORMING GATE DIELECTRIC MATERIAL - A method of forming gate dielectric material includes forming a silicon oxide gate layer over a substrate. The silicon oxide gate layer is treated with a first ozone-containing gas. After treating the silicon oxide gate layer, a high dielectric constant (high-k) gate dielectric layer is formed over the treated silicon oxide gate layer. | 04-19-2012 |
20140080316 | METHODS OF FORMING GATE DIELECTRIC MATERIAL - A method of fabricating a semiconductor device includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing gas through water to treat the silicon oxide layer. The method further includes forming a dielectric layer over the treated silicon oxide layer. | 03-20-2014 |
20150249011 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of cleaning a semiconductor structure includes rotating a semiconductor structure. The method of cleaning further includes cleaning the semiconductor structure with a hydrogen fluoride (HF)-containing gas. A method of forming a semiconductor device includes forming a recess in a source/drain (S/D) region of a transistor. The method of forming further includes cleaning the recess with a HF-containing gas, the HF-containing gas having an oxide removing rate of about 2 nanometer/minute (nm/min) or less. The method of forming further includes epitaxially forming a strain structure in the recess after the cleaning the recess, the strain structure providing a strain to a channel region of the transistor. | 09-03-2015 |
Patent application number | Description | Published |
20080272493 | Semiconductor device - A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer. | 11-06-2008 |
20090258487 | Method for Improving the Reliability of Low-k Dielectric Materials - A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer. | 10-15-2009 |
20090286394 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 11-19-2009 |
20110217840 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 09-08-2011 |
20110263127 | Method for Fabricating Low-k Dielectric and Cu Interconnect - A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch. | 10-27-2011 |
20120077339 | METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING - A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both. | 03-29-2012 |
20130052755 | Automatically adjusting baking process for low-k dielectric material - A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions. | 02-28-2013 |
20130062774 | Semiconductor Device and Method for Forming the Same - A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask. | 03-14-2013 |
20130137261 | METHOD OF MODIFYING A LOW K DIELECTRIC LAYER HAVING ETCHED FEATURES AND THE RESULTING PRODUCT - A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions. | 05-30-2013 |
20130256903 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A interconnect structure includes a conductive layer formed in a dielectric layer. An adhesion layer is formed between the dielectric layer and a substrate. The adhesion layer has a carbon content ratio greater than a carbon content ratio of the dielectric layer. | 10-03-2013 |
20130273732 | METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING - An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller. | 10-17-2013 |
20140141611 | Surface Treatment in the Formation of Interconnect Structure - A Ultra-Violet (UV) treatment is performed on an exposed surface of a low-k dielectric layer and an exposed surface of a metal line. After the UV treatment, an organo-metallic soak process is performed on the exposed surface of the low-k dielectric layer and the exposed surface of the metal line. The organo-metallic soak process is performed using a process gas including a metal bonded to an organic group. | 05-22-2014 |
20150056802 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening in the low-k dielectric layer, forming a conductor in the opening, forming a capping layer over the conductor, and forming an etch stop layer over the capping layer and the low-k dielectric layer. The etch stop layer includes an N element with a content ratio not less than about 25 at %. | 02-26-2015 |
20150155234 | Interconnect Structure and Method for Forming the Same - Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8. | 06-04-2015 |
20150200133 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm. | 07-16-2015 |
Patent application number | Description | Published |
20140184871 | MOBILE DEVICE AND OPTICAL IMAGING LENS THEREOF - Present embodiments provide for a mobile device and an optical imaging lens thereof. The optical imaging lens comprises four lens elements positioned sequentially from an object side to an image side. Though controlling the convex or concave shape of the surfaces, the refraction power and/or the ratio among the parameters of the lens element(s), the optical imaging lens shows better optical characteristics and the total length of the optical imaging lens is shortened. | 07-03-2014 |
20140307148 | OPTICAL IMAGING LENS SET AND ELECTRONIC DEVICE COMPRISING THE SAME - An optical imaging lens set includes: a first lens element with positive refractive power, a second lens element having an image-side surface with a concave portion in a vicinity of its periphery, a third lens element with positive refractive power, having a convex image-side surface, an object-side surface with a concave portion in a vicinity of its periphery, a fourth lens element having a concave object-side surface, and a plastic fifth lens element having an image-side surface with a concave portion in a vicinity of the optical axis. The total thickness T | 10-16-2014 |
20140355136 | MOBILE DEVICE AND OPTICAL IMAGING LENS THEREOF - Present embodiments provide for a mobile device and an optical imaging lens thereof. The optical imaging lens comprises five lens elements positioned sequentially from an object side to an image side. Through controlling the convex or concave shape of the surfaces and/or the refracting power of the lens elements, the optical imaging lens shows better optical characteristics and the total length of the optical imaging lens is shortened. | 12-04-2014 |
20150014515 | MOBILE DEVICE AND OPTICAL IMAGING LENS THEREOF - Present embodiments provide for a mobile device and an optical imaging lens thereof. The optical imaging lens comprises five lens elements positioned sequentially from an object side to an image side. Through controlling the convex or concave shape of the surfaces, the refracting power of the lens elements and two parameters to meet an inequality associated with the thickness of the second lens element, the optical imaging lens shows better optical characteristics and the total length of the optical imaging lens is shortened. | 01-15-2015 |
20150015767 | OPTICAL IMAGING LENS AND ELECTRONIC DEVICE COMPRISING THE SAME - An optical imaging lens set includes a first lens element to a plastic fifth lens element from an object side toward an image side along an optical axis. The second lens element has an image-side surface with a convex portion in a vicinity of its periphery. The fourth lens element has an image-side surface with a concave portion in a vicinity of the optical axis and a convex portion in a vicinity of its periphery. | 01-15-2015 |
20150015772 | Imaging Lens, and Electronic Apparatus Including the Same - An imaging lens includes a first lens element, an aperture stop, and second to fifth lens elements arranged from an object side to an image side in the given order. Through designs of surfaces of the lens elements and relevant optical parameters, a short system length of the imaging lens may be achieved while maintaining good optical performance. | 01-15-2015 |
20150022707 | MOBILE DEVICE AND OPTICAL IMAGING LENS THEREOF - Present embodiments provide for a mobile device and an optical imaging lens thereof. The optical imaging lens comprises five lens elements positioned sequentially from an object side to an image side. Through controlling the convex or concave shape of the surfaces and/or the refracting power of the lens elements, the optical imaging lens shows better optical characteristics and the total length of the optical imaging lens is shortened. | 01-22-2015 |
20150103241 | OPTICAL IMAGING LENS AND ELECTRONIC DEVICE COMPRISING THE SAME - An optical imaging lens set includes a first lens element to a plastic fifth lens element from an object side toward an image side along an optical axis. Each first lens and second lens element has positive refractive power. The third lens element has an image-side surface with a convex portion in a vicinity of the optical axis. The fourth lens element has an image-side surface with a convex portion in a vicinity of the optical axis. The fifth lens element has an image-side surface with a concave portion in a vicinity of the optical axis and a convex portion in a vicinity of its periphery. | 04-16-2015 |
20150103242 | MOBILE DEVICE AND OPTICAL IMAGING LENS THEREOF - Present embodiments provide for a mobile device and an optical imaging lens thereof. The optical imaging lens comprises five lens elements positioned sequentially from an object side to an image side. Through controlling the convex or concave shape of the surfaces of the lens elements and designing parameters satisfying an inequality, the optical imaging lens shows better optical characteristics and the total length of the optical imaging lens is shortened. | 04-16-2015 |
20150103243 | MOBILE DEVICE AND OPTICAL IMAGING LENS THEREOF - Present embodiments provide for a mobile device and an optical imaging lens thereof. The optical imaging lens comprises five lens elements positioned sequentially from an object side to an image side. Through controlling the convex or concave shape of the surfaces and/or the refracting power of the lens elements, the optical imaging lens shows better optical characteristics and the total length of the optical imaging lens is shortened. | 04-16-2015 |
20150103244 | MOBILE DEVICE AND OPTICAL IMAGING LENS THEREOF - The present embodiments provide a mobile device and an optical imaging lens thereof. The optical imaging lens comprises a first lens element, an aperture, a second lens element, a third lens element, a fourth lens element, and a fifth lens element positioned in an order from an object side to an image side. Through controlling the convex or concave shape of the surfaces and/or the refracting power of the lens elements, the total length of the optical image lens is shortened, the field of view is broadened, and the better image performance is maintained. Above all, the optical imaging lens of the present invention is capable of shortening the total length of the optical imaging lens efficiently, enlarging the half field of view of the optical imaging lens, and showing better optical characteristics. | 04-16-2015 |
20150260950 | OPTICAL IMAGING LENS AND ELETRONIC DEVICE COMPRISING THE SAME - An optical imaging lens set, including: a first lens element having an object-side surface with a convex part in a vicinity of the optical axis, and with a convex part in a vicinity of its periphery, a second lens element with negative refractive power, a third lens element with positive refractive power, having an object-side surface with a concave part in a vicinity of its periphery, and having an image-side surface with a convex part in a vicinity of the optical axis, a fourth lens element having an object-side surface with a convex part in a vicinity of its periphery, and having an image-side surface with a concave part in a vicinity of the optical axis, and a convex part in a vicinity of its periphery. | 09-17-2015 |
20150301309 | OPTICAL IMAGING LENS AND ELECTRONIC DEVICE COMPRISING THE SAME - An optical imaging lens includes: a first, second, third and fourth lens element, the first lens element has an object-side surface with a convex part in a vicinity of the optical axis, the second lens element has an image-side surface with a concave part in a vicinity of its periphery; the third lens element has an image-side surface with a convex part in a vicinity of the optical axis, the fourth lens element has an object-side surface with a concave part in a vicinity of the optical axis; the fifth lens element has an object-side surface with a convex part in a vicinity of the optical axis, wherein the optical imaging lens set does not include any lens element with refractive power other than said first, second, third, fourth and fifth lens elements. | 10-22-2015 |