Patent application number | Description | Published |
20110115342 | TUNING FORK QUARTZ CRYSTAL RESONATOR - A tuning fork quartz crystal resonator has a base and two resonating arms extended in parallel from the same side of the base. Each resonating arm has asymmetric grooves on its upper and bottom surface, and the via-hole to reliably connect the top and bottom electrode. The asymmetric groove design can simplify the manufacturing process and lower the manufacturing cost. The base has continuous concave on both side surfaces and a recess on the main surface. The energy of ultrasonic wave propagating via the base mounting pads into the ceramic package can be reduced. This unique tuning fork quartz crystal resonator can prevent dramatic reduction of the Q value, and retain the outstanding quality of the resonator. | 05-19-2011 |
20130154444 | TUNING FORK QUARTZ CRYSTAL RESONATOR - A tuning fork quartz crystal resonator includes a base, a first resonating arm, and a second resonating arm. The base has a generally planar fifth main surface and a generally planar sixth main surface opposite to each other, and has a fifth side surface and a sixth side surface opposite to each other. The first resonating arm is connecting to one side of the base. The second resonating arm is connecting to the same side of the base. A recess is formed on the fifth main surface, and the recess is sized and configured such that a first width near the first resonating arm and the second resonating arm is greater than a second width away from the first resonating arm and the second resonating arm. | 06-20-2013 |
20130169117 | TUNING FORK QUARTZ CRYSTAL RESONATOR - A tuning fork quartz crystal resonator includes a base, a first resonating arm, and a second resonating arm. The base has a generally planar fifth main surface and a generally planar sixth main surface opposite to each other, and has a fifth side surface and a sixth side surface opposite to each other. The first resonating arm is connecting to one side of the base. The second resonating arm is connecting to the same side of the base. A concave of continuous curved surface is formed one each on the fifth side surface and the sixth side surface of the base respectively. | 07-04-2013 |
Patent application number | Description | Published |
20090133742 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - A solar cell includes a substrate, a conductor layer and an anti-reflection coating (ARC) layer. The substrate has a front side, a back side and a doped region adjacent to the front side. The conductor layer has a first portion embedded into the doped region and a second portion other than the first portion. The ARC layer is disposed on the front side of the substrate, the second portion of the conductor layer is disposed in the ARC layer, and the conductor layer has an exposed surface exposed out of the ARC layer. The exposed surface of the conductor layer is substantially flush with an exposed surface of the ARC layer. A method of manufacturing the solar cell is also disclosed. | 05-28-2009 |
20100078068 | SOLAR CELL WITH EMBEDDED ELECTRODE - A solar cell includes a silicon substrate, an anti-reflection coating (ARC) layer, an embedded electrode and a back-side electrode. The silicon substrate has a front side and a back side. The silicon substrate has a P | 04-01-2010 |
20110094571 | SOLAR CELL WITH UPPER AND LOWER CONDUCTOR LAYERS STACKED TOGETHER - A solar cell includes a substrate, a lower conductor layer, an anti-reflection coating (ARC) layer and an upper conductor layer. The substrate has a front side, a back side and a doped region adjacent to the front side. The lower conductor layer has a first portion embedded into the doped region and a second portion other than the first portion. The ARC layer is disposed on the front side of the substrate and covers the lower conductor layer such that the second portion of the lower conductor layer is disposed in the ARC layer. The upper conductor layer has a first portion embedded into the ARC layer and a second portion other than the first portion of the upper conductor layer. The second portion of the upper conductor layer is exposed out of the ARC layer, and the upper conductor layer is electrically connected to the lower conductor layer. | 04-28-2011 |
20120282724 | METHOD OF MANUFACTURING SOLAR CELL WITH UPPER AND LOWER CONDUCTOR LAYERS STACKED TOGETHER - A method of manufacturing a solar cell comprises the steps of: forming a lower conductor layer on a front side of a substrate; firing the lower conductor layer at a first temperature to form a first portion embedded into a doped region of the substrate and a second portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the lower conductor layer such that the second portion is disposed in the ARC layer; forming an upper conductor layer, corresponding to the lower conductor layer and electrically connected to the lower conductor layer, on the ARC layer; and firing the upper conductor layer at a second temperature to form a first portion embedded into the ARC layer and a second portion, which is exposed out of the ARC layer. | 11-08-2012 |
20120288981 | METHOD OF MANUFACTURING SOLAR CELL WITH TWO EXPOSED SURFACES OF ARC LAYER DISPOED AT DIFFERENT LEVELS - A method of manufacturing a solar cell includes the steps of: providing a substrate having a front side, a back side and a doped region; forming a conductor layer on the front side; firing the conductor layer at a temperature such that the conductor layer is formed with a first portion embedded into the doped region and a second portion other than the first portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the conductor layer so that the second portion of the conductor layer is disposed in the ARC layer; and removing the ARC layer on the conductor layer so that the conductor layer has an exposed surface exposed out of the ARC layer, wherein the exposed surface of the conductor layer is substantially flush with a first exposed surface of the ARC layer. | 11-15-2012 |
Patent application number | Description | Published |
20120092300 | VIRTUAL TOUCH SYSTEM - A virtual touch system including a head-mounted see-through display device, a micro-image display, at least two micro image-capturing devices, and an image processing unit is provided. The head-mounted see-through display device has a holder and an optical lens group that allows an image light of a real scene to directly pass through and reach an observing location. The micro-image display disposed on the holder of the head-mounted see-through display device casts a display image to the observing location through the optical lens group to generate a virtual image plane, wherein the virtual image plane contains a digital information. The micro image-capturing devices disposed at the holder capture images of the real scene and a touch indicator. The image processing unit coupled to the head-mounted see-through display device recognizes the touch indicator and calculates a relative location of the touch indicator on the virtual image plane for the micro-image display. | 04-19-2012 |
20140152988 | SYSTEM AND METHOD FOR MEASURING THE ROTATION ANGLE OF OPTICAL ACTIVE SUBSTANCE - A system for measuring the rotation angle of optical active substances has a light source, a polarization generation unit; a polarization analyzing unit; a signal generating unit, respectively and electrically coupled to the polarization generation unit and the polarization analyzing unit; a signal processing unit, electrically coupled to the electric signal generating unit; wherein the light source is enabled to emit a beam toward the polarization generation unit for enabling the beam to be polarized into an incident polarized beam while being projected and traveled in an optical path passing through an optical active substance so as to be converted into a emerging beam; and the polarization analyzing unit is positioned to receive and analyze the emerging beam so as to generate a signal to be received and processed by the signal processing unit. | 06-05-2014 |
20140168417 | INSPECTION DEVICE AND INSPECTION METHOD - The disclosure provides an inspection device including a light source module, an image receiving module and a processing unit. The light source module emits a first incident light and a second incident light to a device under test (DUT). The image receiving module receives a first image corresponding to the DUT irradiated by the first incident light, and receives a second image corresponding to the DUT irradiated by the second incident light. The processing unit calculates the contrast ratio of the first image and the second image to obtain a high-contrast image for inspection. | 06-19-2014 |
Patent application number | Description | Published |
20090168079 | REFLECTIVE FILM THICKNESS MEASUREMENT METHOD - A reflective film thickness measurement method includes reading an original spectral image of a thin film measured by a broadband light source passing through a measurement system, transforming the original spectral image into a broadband reflectance wavelength function and then into a broadband frequency-domain function, dividing the broadband frequency-domain function by a single-wavelength frequency-domain function to obtain an ideal frequency-domain function, inverse-transforming the ideal frequency-domain function into an ideal reflectance wavelength function, and performing a curve fitting on the ideal reflectance wavelength function and a reflectance wavelength thickness general expression, so as to obtain a thickness of the thin film. A spectral image spatial axis direction processing method is performed to eliminate optical aberration in a deconvolution manner, so as to obtain spectral images of high spatial resolution. | 07-02-2009 |
20100085637 | DIFFERENTIAL INTERFERENCE CONTRAST MICROSCOPE - A differential interference contrast microscope (DIC microscope) suitable for inspecting a specimen inside a measurement area comprises a light source, a beam splitter, a first and second polarizer, a first and second DIC prism, a wave plate, and an image sensor, wherein the beam splitter reflects the beam generated from the light source to the measurement area, and the beam be reflected from the measurement area passes through the beam splitter to the image sensor. The first polarizer is located between the light source and the beam splitter, and the second polarizer is located between the beam splitter and the image sensor. The first DIC prism, the wave-plate and the second DIC prism are located between the beam splitter and the measurement area in order. The included angle between the principal axis of the first DIC prism and the principal axis of the second DIC prism is 90 degree. | 04-08-2010 |
20100118293 | PHASE RETARDANCE INSPECTION INSTRUMENT - A phase retardance inspection instrument, comprising: a light source module for generating a single-wavelength light beam; a circularly polarized light generating module, comprising a polarizer and a first phase retarder, for receiving the single-wavelength light beam as it is guided to passe through the polarizer and the first phase retarder in order; and a detecting module, comprising a second phase retarder, a polarizing beam splitter, a first image sensor and a second image sensor, for receiving and guiding a circularly polarized light beam to travel through the second phase retarder and the polarizing beam splitter in order after it passes through a substrate under inspection, wherein the polarizing beam splitter splits an elliptically polarized light beam into intensity vector components of a left-hand circularly polarized light beam and a right-hand circularly polarized light beam, which are to be emitted into the first image sensor and the second image sensor, respectively. | 05-13-2010 |
20100140312 | System For Alignment Measurement For Rolling Embossed Double-Sided Optical Film And Method Thereof - A system for alignment measurement for a rolling embossed double-sided optical film, the system comprising: a first roller with a first brightness enhancement film pattern and a first alignment pattern thereon, a second roller with a second brightness enhancement film pattern and a second alignment pattern thereon; a measuring unit for measuring diffraction patterns in the first alignment region and the second alignment region, respectively; and a control unit electrically connected to the first roller, the second roller and the measuring unit to adjust the relative position between the first roller and the second roller according to the diffraction patterns measured by the measuring unit. | 06-10-2010 |
20110122409 | OBJECT CHARACTERISTIC MEASUREMENT METHOD AND SYSTEM - The present invention provides a method for measuring object characteristics, wherein the method is capable of overcoming the interference induced bye the phase difference of the background with respect to the measuring system so as to measure the tiny characteristics such as the retardance or azimuth angle of an object accurately. The method is capable of obtaining two sets of light intensity images having retardance of background and the object respectively by simultaneously rotating the retarding elements and analyzer in various rotating angle combinations, and analyzing and calculating upon the polarized light intensities of the images associated with the background and the object so as to obtain actual retardance and azimuth angle of the object without the affect of the background retardance. | 05-26-2011 |
Patent application number | Description | Published |
20120295187 | DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS - A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask. | 11-22-2012 |
20140042636 | DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS - A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask. | 02-13-2014 |
20140042640 | DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS - A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns. | 02-13-2014 |
Patent application number | Description | Published |
20120120129 | DISPLAY CONTROLLER DRIVER AND METHOD FOR TESTING THE SAME - A display controller driver and a testing method therewith are provided. The display controller driver includes a timing control circuit, an image data memory, a data line driving circuit and a scan line driving circuit. The testing method includes controlling the scan line driving circuit by a control signal in a test operation mode, wherein the control signal is generated by an external test platform. The scan line driving circuit is tested and measured in accordance with a test pattern of the control signal. | 05-17-2012 |
20120206465 | DISPLAY CONTROLLER DRIVER AND TESTING METHOD THEREOF - A display controller driver and a testing method thereof are provided. The display controller driver includes an image data memory, a timing control circuit, and a data line driving circuit. The image data memory stores display data. The timing control circuit obtains the display data from the image data memory. The data line driving circuit is coupled to the timing control circuit. The data line driving circuit receives the display data and outputs a grayscale voltage signal corresponding to the display data through at least one data-line output terminal of the display controller driver. In a test operation mode, the timing control circuit further transmits the display data from the image data memory to at least one test output port of the display controller driver. | 08-16-2012 |
20120262436 | CONTROLLER DRIVER FOR DRIVING DISPLAY PANEL - A controller driver for driving a display panel is provided. The controller driver comprises a timing control circuit, a data memory unit, a data selection unit and a data line driver circuit. The data memory unit stores image data. The data selection unit coupled to the data memory unit outputs the image data provided from the data memory unit as a display data, or generates the display data in accordance with a command or test patterns provided from an external processor. The data line driver circuit is coupled to the timing control circuit and the data selection unit. The data line driver circuit receives the display data from the data selection unit, and outputs corresponding grayscale voltages according to the control signal outputted from the timing control circuit. | 10-18-2012 |
20140042917 | LED DEVICE, LED DRIVING CIRCUIT AND METHOD - A light-emitting diode (LED) driving circuit includes an LED control circuit and a power stage circuit. The LED control circuit shifts an input pulse width modulation (PWM) signal toward a higher frequency direction in a frequency domain to generate an output PWM signal having a duty cycle substantially the same as a duty cycle of the input PWM signal. The power stage circuit outputs an LED driving current according to the output PWM signal. | 02-13-2014 |
Patent application number | Description | Published |
20110018828 | TOUCH DEVICE, CONTROL METHOD AND CONTROL UNIT FOR MULTI-TOUCH ENVIRONMENT - A touch device for multi-touch environment generates a sensing signal in response to an object touch thereon, generates an event signal according to the sensing signal and a control signal, generates a cursor signal according to coordinate information of each touch point contained in the sensing signal and the event signal, and transmits the cursor signal and the event signal to the multi-touch environment. The cursor signal is used to control a cursor application to show a cursor at a screen for each touch point and changes appearances of the cursors. The cursors clearly inform a user of locations where his/her fingers correspond on the screen. By conducting touch events in the multi-touch environment through the cursors instead of actual fingers, the user can operate the touch device other than a touch screen in a multi-touch manner as operating a multi-touch screen. | 01-27-2011 |
20110022990 | METHOD FOR OPERATION TO A MULTI-TOUCH ENVIRONMENT SCREEN BY USING A TOUCHPAD - A method for operation to a multi-touch environment screen by using a touchpad defines a movable control window on the screen, calculates an inter-window coordinate set of the object mapped from the touchpad to the control window according to an absolute coordinate set of the object on the touchpad and a resolution ratio between the touchpad and the control window when the touchpad is detected being touched, defines a cursor on the screen representative of the object according to the inter-window coordinate set, and changes a coordinate set of the cursor on the screen representative of the object according to a number of the object on the touchpad and movement thereof. This method allows a user to intuitively operate the screen by using the touchpad. | 01-27-2011 |
20120262409 | TOUCH SENSING UNIT HAVING TOUCH SENSING PATTERN WITH HOLLOW AREAS, AND RELATED TOUCH SENSING ELEMENT AND DEVICE USING THE SAME - A touch sensing unit includes an external conductive part and at least one internal conductive part. Each internal conductive part has at least two ends respectively connected to the external conductive part. A sensing pattern constituted by the at least one internal conductive part and the external conductive part includes a plurality of hollow areas. | 10-18-2012 |
Patent application number | Description | Published |
20110018018 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING ELECTRICAL CONNECTION WITHOUT USING WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving electrical connection without using wire-bonding process includes an insulative substrate unit, a package unit, a semiconductor chip, a first conductive unit, an insulative unit and a second conductive unit. The package unit is disposed on the insulative substrate unit to form a receiving groove. The semiconductor chip is received in the receiving groove. The semiconductor chip has a plurality of conductive pads. The first conductive unit has a plurality of first conductive layers formed on the package body, and one side of each first conductive layer is electrically connected to each conductive pad. The insulative unit has an insulative layer formed between the first conductive layers in order to insulate the first conductive layers from each other. The second conductive unit has a plurality of second conductive layers respectively formed on another sides of the first conductive layers. | 01-27-2011 |
20110018019 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FLIP-CHIP TYPE ELECTRICAL CONNECTION WITHOUT USING WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving flip-chip electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a first insulative layer, first conductive layers, a second insulative layer, and second conductive layers. The package unit has a receiving groove. The semiconductor chip is received in the receiving groove and has a plurality of conductive pads disposed on its top surface. The first insulative layer is formed between the conductive pads to insulate the conductive pads. The first conductive layers are formed on the first insulative layer and the package unit, and one side of each first conductive layer is electrically connected to the corresponding conductive pad. The second insulative layer is formed between the first conductive layers in order to insulate the first conductive layers from each other. The second conductive layers are respectively formed on the other opposite sides of the first conductive layers. | 01-27-2011 |
20110229991 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FLIP-CHIP TYPE ELECTRICAL CONNECTION WITHOUT USING WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving flip-chip electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a first insulative layer, first conductive layers, a second insulative layer, and second conductive layers. The package unit has a receiving groove. The semiconductor chip is received in the receiving groove and has a plurality of conductive pads disposed on its top surface. The first insulative layer is formed between the conductive pads to insulate the conductive pads. The first conductive layers are formed on the first insulative layer and the package unit, and one side of each first conductive layer is electrically connected to the corresponding conductive pad. The second insulative layer is formed between the first conductive layers in order to insulate the first conductive layers from each other. The second conductive layers are respectively formed on the other opposite sides of the first conductive layers. | 09-22-2011 |
Patent application number | Description | Published |
20080291150 | Thermal Compensation Device for Display Device - In order to solve a problem of deviation of a gamma curve of a display device due to temperature variation, the present invention provides a thermal compensation device for compensating a gamma curve of a display device. The thermal compensation device includes a thermal sensor, a storage unit, and a thermal compensation unit. The thermal sensor is used for detecting an ambient temperature inside the display device. The storage unit is used for storing a plurality of numerical data groups. The thermal compensation unit is coupled to the thermal sensor and the storage unit is used for selecting one numerical data group from the plurality of numerical data groups and transforming original image data into compensated image data with the selected numerical data group. | 11-27-2008 |
20090115767 | POWER-SAVING MECHANISM OF DISPLAY AND CONTROL METHOD USING THE SAME - A power-saving mechanism of display and a control method using the same are disclosed. The mechanism has no need as the prior art where a user's setting is needed to decide whether or not entering a power-saving operation mode or shutting off the display. The display power-saving mechanism of the present invention can judge whether or not the display frames are still; if the frames are still in a certain time, the display automatically enters the power-saving operation mode. The display power-saving mechanism is disposed in the hardware architecture of the display and capable of automatically judging whether or not to enter the power-saving operation mode without the user's setting. | 05-07-2009 |
20090303217 | TRANSMISSION INTERFACE FOR REDUCING POWER CONSUMPTION AND ELECTROMAGNETIC INTERFERENCE AND METHOD THEREOF - The exemplary examples of the present invention provide a transmission interface and method thereof for reducing power consumption and electromagnetic interference. The transmission interface is used in the Liquid Crystal Display (LCD), and the LCD has x source drivers. The i | 12-10-2009 |
20100171749 | DRIVING APPARATUS OF DISPLAY AND OVER DRIVING METHOD THEREOF - An over driving method for a display is disclosed. The steps of the method mentioned above includes the following. A power saving parameter is set equal to an initial value, a current frame data is received, and a previous frame data is read from a memory. Afterward, the power saving parameter is updated by comparing the current frame data and the previous frame data. Moreover, an over driving process is executed to the display according to the comparison result for the power saving parameter and a reference value. | 07-08-2010 |
20110018888 | ADDRESSING METHOD AND STRUCTURE FOR MULTIPLE CHIPS AND DISPLAY SYSTEM THEREOF - Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of a previous stage is connected to the input enable terminal of a next stage. The method includes setting an initial address to an address of each chip via a system; setting a state of each chip to a disable state; enabling the state of a first-one chip among the chips to an enable state, and setting the first chip as a previous-stage chip; updating the address of the previous-stage chip; enabling a next-stage chip connected after the previous-stage chip, in which the system controls the output enable terminal of the previous-stage chip to output an enable signal to enable the next-stage chip, according to the address of the previous-stage chip; and the updating the address of the next-stage chip. | 01-27-2011 |
20140340384 | DISPLAY DEVICE AND DISPLAY SYSTEM WITH POWER-SAVING MECHANISM - A display device includes an image receiving unit, a power-saving control device, a display control unit, and a backlight module control unit. The power-saving control device judges whether or not received frames are still for a predetermined time. If the power-saving control device judges that the received frames are still for the predetermined time, the power-saving control device outputs a first control signal to the display control unit for controlling the display panel to perform power saving to reduce its power consumption while continuing displaying frames, and the backlight module control unit controls the backlight module to continue providing the backlight; while if the received frames are not still or are still for a time shorter than the predetermined time, the power-saving control device does not output the first control signal to the display control unit for controlling the display panel to perform power saving to reduce its power consumption. | 11-20-2014 |
Patent application number | Description | Published |
20080316199 | CIRCUIT SYSTEM FOR READING MEMORY DATA FOR DISPLAY DEVICE - To reduce power consumption and enhance memory-data transmission efficiency, the present invention provides a circuit system for reading memory data for a display device includes a memory, a data bus and a latch circuit. The memory is used for storing pixel data corresponding to a plurality of pixels and outputting the pixel data according to an output control signal. The data bus is used for transferring the pixel data outputted by the memory. The latch circuit is coupled to the data bus and used for receiving the pixel data from the data bus. The latch circuit includes a plurality of latchers and a plurality of logic circuits. The plurality of latchers is used for storing the pixel data. The plurality of logic circuits is used for performing logic operations on the pixel data stored in the plurality of latchers according to a reading control signal. | 12-25-2008 |
20080320199 | MEMORY AND CONTROL APPARATUS FOR DISPLAY DEVICE, AND MEMORY THEREFOR - A memory and control apparatus and a memory for a display device are provided. The memory and control apparatus includes a memory, a sense-latch circuit, and a timing and memory controlling apparatus. The memory is used for storing data. The memory has a display data bus and a general data bus. The sense-latch circuit is used for sensing and latching the data on the display data bus. The timing and memory controlling apparatus is used for controlling the memory, so as to make the display data represented on the display data bus, and to make the sense-latch circuit outputting the data on the display data bus. When the display device intends to store the data in the memory, the data on the general data bus is stored to the memory. | 12-25-2008 |
20100318753 | MEMORY ARCHITECTURE OF DISPLAY DEVICE AND READING METHOD THEREOF - A memory architecture of a display device including a display data memory block and a processor is provided. The display data memory block includes N sub-memories and N arbiters respectfully coupled to the N sub-memories, wherein N is a positive integer larger than 1. The processor is used for respectfully and continuously outputting corresponding N control signals and N address signals to the N arbiters. After receiving the corresponding control signals, the N arbiters respectfully output the corresponding address signals to corresponding sub-memories, such that the N sub-memories simultaneously access data respectfully according to the N address signals. | 12-16-2010 |
20110153923 | HIGH SPEED MEMORY SYSTEM - A high speed memory system includes a plurality of memory devices; a plurality of buffers; and a memory controller. The plurality of buffers is respectively coupled to the plurality of memory devices. The memory controller is coupled to the plurality of buffers, for generating a plurality of control signal to the plurality of buffers and sequentially controlling access to the plurality of memory devices in a time-sharing manner according to a clock. | 06-23-2011 |
20110169870 | Method and Device for Cancelling Deviation Voltage of a Source Driver of a Liquid Crystal Display - A method for cancelling the deviation voltage of a source driver of a LCD is disclosed. The method includes measuring an effective load resistor and an effective load capacitor of a panel of the LCD against the source driver, computing a lowest valid frequency of the chopper circuit according to the effective load resistor and the effective load capacitor, and adjusting the switching frequency of the chopper circuit according to the lowest valid frequency to filter out high frequency components of signals outputted by the source driver via the panel, so as to cancel the deviation voltage. | 07-14-2011 |
20110187757 | SOURCE DRIVING APPARATUS FOR DISPLAY - A source driving apparatus of a display is disclosed. The source driving apparatus includes a digital-to-analog converter, a selecting signal generator and a voltage selector. The digital-to-analog converter receives a first part display signal of a display signal and a plurality of gamma voltages and selects a first selecting gamma voltage and a second selecting gamma voltage within the gamma voltages according to the first part display signal. The selecting signal generator receives a second part display signal of the display signal expect the first part display signal and a plurality of pulse-width-modulation (PWM) signals. The selecting signal generator selects one of the PWM signals to generate a selecting signal according to the second part display signal. The voltage selector outputs the first selecting gamma voltage or the second selecting gamma voltage according to a pulse width of the selecting signal. | 08-04-2011 |
Patent application number | Description | Published |
20120007198 | BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated (BSI) image sensor including a substrate, a plurality of photosensitive regions, a back-end-of-line (BEOL), a pad, a color filter array, a plurality of micro-lenses and a protection layer is provided. The substrate has a first surface and a second surface. The substrate has a pad opening therein through the first surface and the second surface. The photosensitive regions are disposed in the substrate. The BEOL is disposed on the first surface of the substrate. The pad is disposed in the BEOL and exposed by the pad opening. The color filter array is disposed on the second surface of the substrate. The micro-lenses are disposed on the color filter array. The protection layer at least covers the top corner and the sidewall of the pad opening. | 01-12-2012 |
20130312246 | METHOD FOR SUPPORTING SEMICONDUCTOR WAFER AND WAFER SUPPORTING ASSEMBLY - A method for supporting a semiconductor wafer includes providing a device wafer to a magnetizable ring, providing a magnetizable carrier to the device wafer, and magnetizing the magnetizable ring and the magnetizable carrier to form a magnetized clamp having a magnetized ring and magnetized carrier. The magnetized clamp securely clamps the device wafer therebetween. | 11-28-2013 |
20130313691 | THINNED WAFER AND FABRICATING METHOD THEREOF - A thinning method of a wafer is provided. The method includes the following steps. First, a wafer having a first surface, a second surface, and a side surface is provided, and the side surface is connected between the first surface and the second surface. At least one semiconductor device is formed on the first surface. Then, an anisotropy etching process is performed to the second surface with a mask to remove portions of the wafer while remaining the side surface thereby forming a number of grooves in the second surface and at least one reinforcing wall between the grooves. As a result, a thinned wafer is obtained. | 11-28-2013 |
Patent application number | Description | Published |
20120039129 | COST SAVING ELECTRICALLY-ERASABLE-PROGRAMMABLE READ-ONLY MEMORY (EEPROM) ARRAY - A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line. | 02-16-2012 |
20120039131 | LOW-VOLTAGE EEPROM ARRAY - A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines. | 02-16-2012 |
20120040504 | METHOD FOR INTEGRATING DRAM AND NVM - The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanting ion into regions of the semiconductor substrate, which are at two sides of the first gate insulation layer, to form two heavily-doped areas that are adjacent to the first gate insulation layer and respectively function as a drain and a source; respectively forming over the first gate layer a second gate insulation layer and a second gate layer functioning as a control gate. The present invention not only increases the transmission speed but also reduces the power consumption, the fabrication cost and the package cost. | 02-16-2012 |
Patent application number | Description | Published |
20080302073 | Can-filter structure of oxygen concentrator - The invention is a can-filter structure of an oxygen concentrator, which includes: a first can-filter having filter material; a second can-filter having filter material; and an outlet cover. The first can-filter includes an air inlet provided at the entrance side of the first can-filter and a first conical joint formed at the exit side of the first can-filter, wherein the first conical joint is hollow and at least one recess is provided on the outer surface thereof. The second can-filter includes a second conical joint formed at the entrance side of the second can-filter, wherein the second conical joint is hollow, and at least one engaging hook corresponding to the recess is provided on the inner surface thereof for coupling to the first conical joint. The outlet cover is provided at the exit side of the second can-filter and is coupled thereto by ultrasonic fusion. | 12-11-2008 |
20080314006 | Quickly assemblable structure of molecular sieves and can filters in oxygen concentrator - The invention is an assembly structure that allows molecular sieves and can-filters be fast assembled in an oxygen concentrator. The structure includes: a molecular sieve and can-filter set, which is composed of at least two molecular sieves and at least one can-filter; a support frame, which includes a base plate and a frame fixed on the base plate in an upright position, and the frame has a first support plate having a plurality of through holes and a second support plate having a hole, wherein the hole of the second support plate is for one of the at least one can-filter to pass through; and a plurality of bend joints, each of which including: a thin plate portion formed at a first end, wherein an opening is provided in the center of the thin plate portion; and a plurality of annular barbed portions provided near a second end, such that a flexible conduit/hose connected thereto does not detach easily and the air tightness is increased, wherein the second end of each bend joint passes through one of the through holes of the first support plate while the thin plate portion of each bend joint is fixed to the first support plate via a second fastener. | 12-25-2008 |
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20090021643 | DIGITAL TELEVISION CHIP, SYSTEM AND METHOD THEREOF - A digital television chip having a reduced layout size is disclosed, comprising a multiplexer, and first and second converting units. The multiplexer, according to a control signal, outputs one of S-video signals SY and SC to the first converting unit, outputs the other of the S-video signals SY and SC to the second converting unit, outputs one of Tuner CVBS signals VIF and SIF to the first converting unit, outputs the other of the Tuner CVBS signals VIF and SIF to the second converting unit, or outputs a CVBS Line-in Video signal to one of the first and second converting units, for reducing the size of the chip. The first converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a first digital signal for signal processing. The second converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a second digital signal for signal processing. | 01-22-2009 |
20090289821 | PIPELINE ANALOG-TO-DIGITAL CONVERTER HAVING OPERATIONAL AMPLIFIER SHARED BY SAMPLE AND HOLD CIRCUIT AND LEADING MULTIPLYING DIGITAL-TO-ANALOG CONVERTER - A pipeline analog-to-digital converter includes a sample and hold circuit; a plurality of multiplying digital-to-analog converters having a leading MDAC coupled to the sample and hold circuit; and an operational amplifier, shared by the sample and hold circuit and the leading MDAC. The shared operational amplifier configured to be used by the sample and hold circuit when the sample and hold circuit enters a hold phase and used by the leading MDAC when the sample and hold circuit enters a sample phase can greatly reduce the power consumption of the pipeline ADC. | 11-26-2009 |
20100073209 | TRACK AND HOLD AMPLIFIERS AND ANALOG TO DIGITAL CONVERTERS - A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal. | 03-25-2010 |
20100225515 | TRACK AND HOLD AMPLIFIERS AND ANALOG TO DIGITAL CONVERTERS - A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal. | 09-09-2010 |
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20100123255 | ELECTRONIC PACKAGE STRUCTURE AND METHOD - An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken. | 05-20-2010 |
20100124801 | ELECTRONIC PACKAGE STRUCTURE AND METHOD - An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken. | 05-20-2010 |
20100129962 | ELECTRONIC PACKAGE STRUCTURE AND METHOD - An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken. | 05-27-2010 |
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20110248359 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer. | 10-13-2011 |
20130288456 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed. | 10-31-2013 |
20140248762 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed. | 09-04-2014 |