Patent application number | Description | Published |
20110157839 | ELECTRONIC DEVICE, FILTERING MODULE THEREOF AND METHOD FOR REDUCING COMMON MODE NOISE - A filtering module includes a circuit board, a connector, a core and a plurality of coils. The connector and the core are disposed on the circuit board. The coils wind around the core and are electrically connected to the connector. | 06-30-2011 |
20110162878 | ELECTRONIC DEVICE AND EMI/ESD PROTECTION MODULE THEREOF - An EMI/ESD protection module is disposed between a first metal connecting member and a second metal connecting member. The EMI/ESD protection module includes a first conductive member, a second conductive member and a resilient member. The first conductive member is electrically connected to the first metal connecting member. The second conductive member is movably connected to the first conductive member and electrically connected to the second metal connecting member. The resilient member is disposed between the first and second conductive members. | 07-07-2011 |
20110181432 | EXTERNAL DEVICE HAVING LOW POWER DETECTION AND PROTECTION AND METHOD THEREOF - When an external device connects to a connecting port of a host, a current detection circuit of the external device detects if the current provided by the host is less than the working current needed by the external device. If the current provided by the host is insufficient to initialize and operate the external device, a controller of the external device then stop powering the main component of the external device so that the main component will not damage due to constantly start/stop and can be protected. Meanwhile, an indicator of the external device notifies the insufficiency of current provision by vibrating, beeping, or displaying an indicating signal. Illusion of failure of the external device may be effectively avoided. | 07-28-2011 |
20110191358 | FILE FORMAT CONVERSION SYSTEM AND METHOD THEREOF - A file format conversion system includes a web server, a service providing server and an electronic device. The web server provides a first URL associated with a first file. The electronic device sends a request of the first URL to the service providing server. The service providing server analyzes the first URL based on the request and generates a first list, which records file formats stored at the first URL. The electronic device separates the first list into a second list, which records file formats supported by the electronic device, and a third list, which records file formats not supported by the electronic device. After receiving the second and third list, the service providing server updates two databases inside. The service providing server converts the first file into a second file based on the second and third lists and generates a second URL associated with the second file. | 08-04-2011 |
20110246204 | IMAGE DISPLAY DEVICE AND METHOD THEREOF - An image display device includes a display unit, a storage unit, a voice receiving unit and a processing unit. The storage unit stores a plurality of image data, a plurality of voice data and a plurality of image files, wherein each of the image data is corresponding to one of the voice data respectively. The voice receiving unit receives a current voice. The processing unit judges whether the current voice is similar to one of the voice data, so as to determine one image data corresponding to the current voice. When the current voice is similar to one of the voice data, the processing unit determines whether each of the image files contains the image data corresponding to the current voice and then displays the image file(s), which contain the image data corresponding to the current voice, on the display unit. | 10-06-2011 |
Patent application number | Description | Published |
20110082239 | THERMOSETTING EPOXY COMPOSITION WITH LOW EXPANSIBILITY - A thermosetting epoxy composition contains a modified silicon dioxide and is suitable for use in preparing an epoxy laminate having a low coefficient of thermal expansion and good drilling workability, which modified silicon dioxide contains no crystal water, has low expansibility, and contains 40% to 80% by weight of silicon dioxide and 60% to 20% by weight of an inorganic additive, and the modified silicon dioxide is obtained by a high-temperature (above 1000° C.) sintering process followed by a crushing process. | 04-07-2011 |
20110092640 | COMPOSITION OF MODIFIED MALEIC ANHYDRIDE AND EPOXY RESIN - The present invention provides a composition of the modified maleic anhydride and the epoxy resins, including (A) one or more of the epoxy resin mixtures, (B) a modified maleic anhydride copolymer, (C) additives and (D) inorganic filler materials, wherein component (A) the epoxy resin mixture accounts for 35%˜56% by weight of the composition solids, component (B) the modified maleic anhydride copolymer accounts for 44%˜65% by weight of the composition solids, based on 100% by weight of total components (A), (B) and (C). According to the present invention, the modified maleic anhydride copolymer curing agent is prepared by reacting styrene/maleic anhydride copolymer with a modifier having hydroxy groups (OH), wherein the modifier having hydroxy groups (OH) can be a brominated, phosphorus-based or halogen-free material; the epoxy resin composition of the present invention shows good heat resistance and outstanding electrical properties, is suitable for the production of prepreg material, bonding films and copper clad laminates, thus can be used in the field of the general or high-frequency printed circuit boards. | 04-21-2011 |
20110306725 | VARNISH COMPOSITION WITH HIGH TEMPERATURE OF GLASS TRANSITION FOR GLASS FIBER LAMINATE - A varnish composition includes (1) a benzoxazine resin having highly symmetric molecular structure; (2) at least one of naphthol type novolac resins, aniline type novolac resins and phenolic type novolac resins; (3) fillers. The benzoxazine resin having highly symmetric molecular structure, and the at least one of naphthol type novolac resins, aniline type novolac resins and phenolic type novolac resins contribute to increase the temperature of glass transition of the varnish composition, while decrease the coefficient of thermal expansion and moisture absorbability due to their small and highly symmetric molecular structures. A copper substrate can meet the requirement of high temperature of glass transition (TMA≧200° C.) and low coefficient of thermal expansion (α1/α≦30/1350(μm/(m° C.). Therefore, the composition of the invention can be widely used as high-performance electronic material. | 12-15-2011 |
20130092548 | PROCESS TO MANUFACTURE SURFACE FINE GRAIN COPPER FOIL WITH HIGH PEELING STRENGTH AND ENVIRONMENTAL PROTECTION FOR PRINTED CIRCUIT BOARDS - The present invention relates to a manufacturing method for a fine grain surface copper foil with the low roughness, high peeling strength, high chemical resistance, high heat resistance, high resistance to moisture absorption and good etching properties, and applicable to all kinds of printed circuit boards. The technical characteristics are that the adhesion surface of copper foil is electroplated in an electroplating bath composed of copper sulfate, sulfuric acid, tungsten compounds to obtain a roughening treatment layer which is then treated with a electroplating copper foil method for anti-rust and thermoresistance known to the art to get a Zn alloy thermoresistant layer. | 04-18-2013 |
20140141274 | COPPER FOIL STRUCTURE HAVING BLACKENED ULTRA-THIN FOIL AND MANUFACTURING METHOD THEREOF - A copper foil structure having blackened ultra-thin copper foil of the instant disclosure includes a carrier foil, a blackened layer, a release layer, and an ultra-thin copper foil. The carrier foil includes a matte surface and a shiny surface wherein the blackened layer is disposed thereon. The release layer is disposed on the blackened layer formed with one selected from the group: copper, cobalt, nickel, and manganese while the release layer is formed with one selected from the group: molybdenum, nickel, chromium, and potassium. Successively, the ultra-thin copper foil is disposed on the release layer. Laser drilling can apply to the blackened ultra-thin copper foil on the inner layers of a high density multi-layer printed wiring board, thus eliminating the traditional blackening or browning chemical process. The blackened ultra-thin copper foil in combination with a polyimide thin (PI) or other substrate materials displays desirable appearance. | 05-22-2014 |
20140220373 | COMPOSITE DUAL BLACKENED COPPER FOIL AND METHOD OF MANUFACTURING THE SAME - A composite dual blackened copper foil includes a copper foil and two blackened layers. The copper foil has a shiny side and a matte side. The blackened layers are formed on the shiny and matte sides respectively. The blackened layers are formed alloy by electroplating in a plating bath consisting essentially of copper, cobalt, nickel, manganese, magnesium and sodium ions. A rough layer is selectively formed between the blackened layer and the shiny side as well as the matte side. Both side of the copper foil is spotless, powder free, and good in etching quality. The copper foil is effective at blocking electromagnetic wave, near infrared, undesired light and the like. The copper foil exhibits strong light absorption and is applicable to direct gas laser drilling. A method of manufacturing the composite dual blackened copper foil is also provided. | 08-07-2014 |
20150068912 | COPPER FOIL STRUCTURE HAVING BLACKENED ULTRA-THIN FOIL AND MANUFACTURING METHOD THEREOF - A copper foil structure having blackened ultra-thin copper foil of the instant disclosure includes a carrier foil, a blackened layer, a release layer, and an ultra-thin copper foil. The carrier foil includes a matte surface and a shiny surface wherein the blackened layer is disposed thereon. The release layer is disposed on the blackened layer formed with one selected from the group: copper, cobalt, nickel, and manganese while the release layer is formed with one selected from the group: molybdenum, nickel, chromium, and potassium. Successively, the ultra-thin copper foil is disposed on the release layer. Laser drilling can apply to the blackened ultra-thin copper foil on the inner layers of a high density multi-layer printed wiring board, thus eliminating the traditional blackening or browning chemical process. The blackened ultra-thin copper foil in combination with a polyimide thin (PI) or other substrate materials displays desirable appearance. | 03-12-2015 |
Patent application number | Description | Published |
20100311916 | ELECTRIC CIRCUIT BOARD COMPOSITION AND A METHOD OF PREPARING CIRCUIT BOARD - The present invention provides a new epoxy resin which is modified with halide and oxazolidone ring. This epoxy resin can improve the peeling strength, Tg, heat resistance, and flame resistance for CCL and be used for print circuit board. The composition comprising (A) a halogen-containing epoxy which containing a oxazolidone ring, about 5˜95 wt % of total weight, (B) epoxy resins with two or above epoxy groups, about 95˜5 wt % of total weight, (C) a curing agent, example of phenol novolac, and (D) a curing accelerator. After laminating the prepreg which had been made by impregnation of the mentioned composition at 170˜210 with 10˜30k gf/cm | 12-09-2010 |
20110224345 | NOVEL LOW DIELECTRIC RESIN VARNISH COMPOSITION FOR LAMINATES AND THE PREPARATION THEREOF - This invention relates to a low dielectric resin varnish composition for laminated printed circuit boards, wherein the resin composition includes (A) Dicyclo-pentadiene-Phenolic Novolac resin (abbreviated as DCPD-PN); or (B) at least one kind of dicyclopentadiene Phenolic Novolac Epoxy resins(DCPD-PNE, referred to as Resin 1); or (C) a novel Dicyclopentadiene-Dihydrobenzoxazine resin (DCPD-BX, referred to as Resin 2); or the mixture of (B) and (C), and (D) Flame retardant agent, curing agent and accelerating agent solutions. | 09-15-2011 |
20110245431 | LOW DIELECTRIC BROMINATED RESIN WITH A SYMMETRIC OR SATURATED HETEROCYCLIC ALPHATIC MOLECULAR STRUCTURE AND THE PREPARATION THEREOF - The present invention provides a brominated epoxy resin, which has a molecular segment of low polarity in the polymer chain, while the molecular segment of low polarity is attributed to the symmetric or saturated cyclic alphatic molecular structure with low “molecular dipole moment” characteristics; making a printed circuit board for high frequency signal transformation applications needs a proper copper clad laminate which processes the properties of a low dielectric constant and of a low dissipation factor; a copper clad laminate can meet above requirements by using the inventive resin as a laminate binder. The inventive resin is prepared by the following steps:
| 10-06-2011 |
20110315435 | ACID ANHYDRIDE CURABLE THERMOSETTING RESIN COMPOSITION - The present invention provides a resin composition suitable for printed circuit boards, the composition includes one epoxy resin or the mixture thereof, curing agent, promoting agents and additives, wherein the ratio of curing agent to epoxy resin is 1.55˜2.5, in which epoxy resin consists of at least one of phenol-formaldehyde multi-functional epoxy resin; curing agent comprises at least one of styrene-maleic anhydride copolymer. After hardening, this resin composition has excellent electrical properties, high glass transition temperature and excellent heat-resistant properties, applicable to the lead-free printed circuit board manufacturing process, and in the field of the high-frequency and packaging-board containing printed circuit boards. | 12-29-2011 |
Patent application number | Description | Published |
20100105205 | CLEANING SOLUTION AND SEMICONDCUTOR PROCESS USING THE SAME - A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. | 04-29-2010 |
20120070948 | ADJUSTING METHOD OF CHANNEL STRESS - An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region. | 03-22-2012 |
20120086054 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties. | 04-12-2012 |
20120223397 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ. | 09-06-2012 |
20120231600 | SEMICONDUCTOR PROCESS HAVING DIELECTRIC LAYER INCLUDING METAL OXIDE AND MOS TRANSISTOR PROCESS - A semiconductor process having a dielectric layer including metal oxide is provided. The semiconductor process includes: A substrate is provided. A dielectric layer including metal oxide is formed on the substrate, wherein the dielectric layer has a plurality of oxygen-related vacancies. A first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen. Otherwise, three MOS transistor processes are also provided, each of which has a gate dielectric layer including a high dielectric constant, and a first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen. | 09-13-2012 |
20120264279 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, wherein the method comprises steps as follows: a semiconductor structure comprising a substrate, a dummy gate structure having a dielectric layer disposed over the substrate and a silicon layer disposed over the dielectric layer, and an etching stop layer (ESL) and an inter-layer dielectric (ILD) layer both of which are sequentially disposed over the substrate and the dummy gate structure is first provided. Then, a chemical mechanical polishing (CMP) is performed to planrizing the ILD layer and expose the ESL. Subsequently, an in-situ etching process is conducted to remove portions of the ESL and the silicon layer to form an opening in the dummy gate structure. Next, metal material is filled into the opening. | 10-18-2012 |
20150380512 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ. | 12-31-2015 |
Patent application number | Description | Published |
20140327055 | REPLACEMENT GATE PROCESS AND DEVICE MANUFACTURED USING THE SAME - A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench. | 11-06-2014 |
20140349452 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES - A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer. | 11-27-2014 |
20140361352 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric. | 12-11-2014 |
20150052491 | METHOD FOR GENERATING LAYOUT PATTERN - A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns. | 02-19-2015 |
20150064929 | METHOD OF GAP FILLING - A method of gap filling includes providing a substrate having a plurality of gaps formed therein. Then, an in-situ steam generation oxidation is performed to form an oxide liner on the substrate. The oxide liner is formed to cover surfaces of the gaps. Subsequently, a high aspect ratio process is performed to form an oxide protecting layer on the oxide liner. After forming the oxide protecting layer, a flowable chemical vapor deposition is performed to form an oxide filling on the oxide protecting layer. More important, the gaps are filled up with the oxide filling layer. | 03-05-2015 |
20150076623 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region. | 03-19-2015 |
20150093870 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE STRUCTURE - A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer. | 04-02-2015 |
20150129980 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure comprises a substrate, a plurality of fins, an oxide layer and a gate structure. The fins protrude from the substrate and are separated from each other by the oxide layer. The surface of the oxide layer is uniform and even plane. The gate structure is disposed on the fins. The fin height is distance between the top of the fins and the oxide layer, and at least two of the fins have different fin heights. | 05-14-2015 |
20150147874 | METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE - The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin. | 05-28-2015 |
20150179457 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PATERNED HARD MASK - A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric. | 06-25-2015 |
20150206759 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation. | 07-23-2015 |
20150347657 | METHOD FOR GENERATING LAYOUT PATTERN - A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask. | 12-03-2015 |
20150380506 | REPLACEMENT GATE PROCESS AND DEVICE MANUFACTURED USING THE SAME - A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench. | 12-31-2015 |
20160027892 | METAL GATE STRUCTURE - The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer. | 01-28-2016 |
20160035854 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region. | 02-04-2016 |
20160071800 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via. | 03-10-2016 |
20160099179 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed. | 04-07-2016 |
20160104645 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures. | 04-14-2016 |
Patent application number | Description | Published |
20090072325 | METAL-OXIDE SEMICONDUCTOR TRANSISTOR - A metal-oxide semiconductor (MOS) transistor includes a gate structure positioned in an active area defined in a substrate, a recessed source/drain, and an asymmetric shallow trench isolation (STI) for electrically isolating the active areas. A surface of the asymmetric STI and the substrate is coplanar. | 03-19-2009 |
20090075441 | Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device - A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer. | 03-19-2009 |
20110068408 | STRAINED-SILICON CMOS TRANSISTOR - A strained-silicon CMOS transistor includes: a semiconductor substrate having a first active region, a second active region, and an isolation structure disposed between the first active region and the second active region; a first transistor, disposed on the first active region; a second transistor, disposed on the second active region; a first etching stop layer, disposed on the first transistor and the second transistor; a first stress layer, disposed on the first transistor; a second etching stop layer, disposed on the first transistor and the first stress layer, wherein an edge of the first stress layer is aligned with that of the second etching stop layer; a second stress layer, disposed on the second transistor; and a third etching stop layer disposed on the second transistor and the second stress layer, wherein an edge of the second stress layer is aligned with that of the third etching stop layer. | 03-24-2011 |
20110076814 | METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR - First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region. | 03-31-2011 |
20130087861 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer. | 04-11-2013 |
20140099760 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed. | 04-10-2014 |