Patent application number | Description | Published |
20080259688 | Non-volatile memory devices and methods of operating the same - A non-volatile memory device includes memory transistors disposed on a semiconductor substrate in a NAND string. A string select transistor is disposed at a first end of the NAND string, and a ground select transistor is disposed at a second end of the NAN string. Bit lines are electrically connected to the semiconductor substrate outside of the string select transistor and a gate electrode of the ground select transistor. | 10-23-2008 |
20080315285 | Non-volatile memory devices and methods of fabricating the same - Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode. | 12-25-2008 |
20090016107 | Methods of operating nonvolatile memory devices - Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell. | 01-15-2009 |
20090091975 | Non-volatile memory device and operation method of the same - Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. | 04-09-2009 |
20090122613 | Non-volatile memory device and method of operating the same - A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings. | 05-14-2009 |
20090212320 | Semiconductor devices and semiconductor apparatuses including the same - Semiconductor devices and semiconductor apparatuses including the same are provided. The semiconductor devices include a body region disposed on a semiconductor substrate, gate patterns disposed on the semiconductor substrate and on opposing sides of the body region, and first and second impurity doped regions disposed on an upper surface of the body region. The gate patterns may be separated from the first and second impurity doped regions by, or greater than, a desired distance, such that the gate patterns do not to overlap the first and second impurity doped regions in a direction perpendicular to the first and second impurity doped regions. | 08-27-2009 |
20090212364 | Semiconductor substrates and manufacturing methods of the same - Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region. | 08-27-2009 |
20090230442 | Semiconductor apparatus and manufacturing method of the same - Provided is a semiconductor apparatus including a substrate region, an active region on the substrate region, a gate pattern on the active region, and first and second impurities-doped regions along both edges of the active region that do not overlap the gate pattern. The length of the first and second impurities-doped regions in the horizontal direction may be shorter than in the vertical direction. The first and second impurities-doped regions may be formed to be narrow along both edges of the active region so as not to overlap the gate pattern. | 09-17-2009 |
20090285027 | Non-volatile memory devices and methods of operating non-volatile memory devices - A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line. | 11-19-2009 |
20090315084 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE - A semiconductor device includes a semiconductor substrate, a gate pattern disposed on the semiconductor substrate, a body region disposed on the gate pattern and a first impurity doping region and a second impurity doping region. The gate pattern is disposed below the body region and the first impurity doping region and the second impurity doping region. | 12-24-2009 |
20100027316 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided. | 02-04-2010 |
20100038719 | Semiconductor apparatuses and methods of manufacturing the same - Disclosed are semiconductor apparatuses and methods of fabricating the same. According to the methods, the number of operations for fabricating the semiconductor apparatuses having a plurality of layers may be the same as the number of operations for fabricating a semiconductor apparatus having one layer. The semiconductor apparatuses may include first active regions extending in the same direction, in parallel, separated from each other and including first and second impurity doped regions on opposite ends of the first active regions from each other. The semiconductor apparatuses may further include second active regions on a layer above the first active regions, extending in the same direction as the first active regions, separated from each other, in parallel, and including first and second impurity doped regions on opposite ends of the second active regions from each other. | 02-18-2010 |
20100097124 | Method of operating semiconductor device - Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse. | 04-22-2010 |
20100118623 | Method of operating semiconductor devices - A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device. | 05-13-2010 |
20100118634 | Semiconductor apparatuses and methods of operating the same - A method of operating a semiconductor device is provided including applying a constant source voltage to a source line. | 05-13-2010 |
20100127759 | Method of operating semiconductor device - Provided is a method of operating a semiconductor device, in which a gate voltage or a drain voltage is adjusted in order to add carriers to or remove carriers from a body region, thereby realizing semiconductor having a plurality of data states. | 05-27-2010 |
20100133600 | Semiconductor devices having increased sensing margin - One transistor (1-T) dynamic random access memories (DRAM) having improved sensing margins that are relatively independent of the amount of carriers stored in a body region thereof. | 06-03-2010 |
20100133647 | Semiconductor devices and semiconductor device manufacturing methods - Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure. | 06-03-2010 |
20100135088 | Operation method of semiconductor device - Provided is a method of operating a semiconductor device, in which timing for switching each of a drain voltage pulse signal and a gate voltage pulse signal from a first state to a second state is controlled in an erase mode and a write mode. | 06-03-2010 |
20100177566 | Non-volatile memory device having stacked structure, and memory card and electronic system including the same - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set. | 07-15-2010 |
20100296344 | Methods of operating nonvolatile memory devices - Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell. | 11-25-2010 |
20110121390 | Semiconductor substrates and manufacturing methods of the same - Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region. | 05-26-2011 |
20110181781 | METHOD AND APPARATUS FOR DISPLAYING VIDEO SIGNALS FROM A PLURALITY OF INPUT SOURCES - Provided are an apparatus and method thereof for displaying video signals on a display screen of a display apparatus, wherein the video signals are received by the display apparatus from a plurality of input sources. The method includes: determining whether a medium input from a first input source of the display apparatus is in a loading process; if the medium is in the loading process, displaying in a sub-window on the display screen a video signal output from the first input source of the display apparatus; if the medium is in the loading process, displaying in a main window on the display screen a video signal output from a second input source of the display apparatus. The video signal from the first input source may be downscaled and transmitted to the display device so as to conserve resources in both the first input source and the display device. | 07-28-2011 |
20110205224 | CONTENT REPRODUCING APPARATUS AND CONTROL METHOD THEREOF - Disclosed herein are a content reproducing apparatus to display a content image and a menu image on a display device, and a control method thereof. The menu image is generated based on a support capability of the display device. Therefore, when the content image and the menu image are alternately displayed, screen flickering may be prevented from occurring due to a change in image format. Also, a support capability of each constituent element may be notified to the user as guide information, and the content image may be output after user confirmation. | 08-25-2011 |
20120137335 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD THEREOF - An image processing method, includes: receiving streaming contents; extracting definition control information which includes content provider information and corresponds to the streaming contents; and controlling definition of the streaming contents by using the extracted definition control information. | 05-31-2012 |
20120161277 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE MANUFACTURING METHODS - Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure. | 06-28-2012 |
20130161727 | NON-VOLATILE MEMORY DEVICE HAVING STACKED STRUCTURE, AND MEMORY CARD AND ELECTRONIC SYSTEM INCLUDING THE SAME - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set. | 06-27-2013 |
20140376880 | IMAGE DISPLAY SYSTEM AND DISPLAY METHOD THEREOF - An image display system and a display method thereof are provided. The image display system includes an optical disc having image information thereon, an image display device having extended display identification data (EDID), and a reproduction device to analyze the EDID to determine an interface to connect with the image display device, if the image information is three-dimensional (3D) image information, and instruct the image display device to output an alarm text, if the interface is an analog. When the interface is an analog interface, the reproduction device may output an analog two-dimensional (2D) image or 3D image through the image display device. Even when the image display device and the reproduction device are interconnected via an analog interfaces, a 2D or 3D image may be output based on the 3D image information. | 12-25-2014 |