Patent application number | Description | Published |
20080237647 | Integrated Circuits and Methods with Two Types of Decoupling Capacitors - Methods and systems for optimal decoupling capacitance in a dual-voltage power-island architecture. In low-voltage areas of the chip, accumulation capacitors of two different types are used for decoupling, depending on whether the capacitor is located in an area which is always-on or an area which is conditionally powered. | 10-02-2008 |
20080238555 | Systems, Modules, Chips, Circuits and Methods with Delay Trim Value Updates on Power-Up - Timing measurement is performed by a digital oscillator, using a calibration value which is calculated after chip fabrication is completed, and automatically loaded into selection logic at powerup. | 10-02-2008 |
20080297961 | Systems, Circuits, Chips and Methods with Protection at Power Island Boundaries - Integrated circuits where the standard isolation cell, at power island boundaries, also includes a protection device, which clamps transient voltages. | 12-04-2008 |
20130300485 | APPARATUS AND METHOD FOR HIGH VOLTAGE SWITCHES - Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor. | 11-14-2013 |
20150054565 | Systems and Methods for Operating High Voltage Switches - A system for communicating high voltages for a semiconductor device is provided. One system includes a controller having an input pad and an output pad, each of the input pad and the output pad being coupled to a respective high voltage switch of the controller. The system also includes a plurality of semiconductor chips, where each of the plurality of semiconductor chips has at least one input pad coupled to a high voltage switch of a respective semiconductor chip. A high voltage that is higher than normal operation voltages of the semiconductor device is coupled from the input pad of the controller to the output pad of the controller via the coupled high voltage switches of the controller. The high voltage is further coupled from the output pad of the controller to the at least one input pad of the respective semiconductor chip via the high voltage switch coupled to the at least one input pad of the respective semiconductor chip. Methods for operating and providing high voltage inputs to one or more semiconductor devices are also provided. | 02-26-2015 |
Patent application number | Description | Published |
20100082787 | Global server load balancing - A global server load-balancing (GSLB) switch serves as a proxy to an authoritative DNS and communicates with numerous site switches that are coupled to host servers serving specific applications. The GSLB switch receives from site switches operational information regarding host servers within the site switches neighborhood. When a client program requests a resolution of a host name, the GSLB switch, acting as a proxy of an authoritative DNS, returns one or more ordered IP addresses for the host name. The IP addresses are ordered using metrics that include the information collected from the site switches. In one instance, the GSLB switch places the address that is deemed “best” at the top of the list. | 04-01-2010 |
20100121932 | Distributed health check for global server load balancing - A global server load-balancing (GSLB) switch serves as a proxy to an authoritative DNS and communicates with numerous site switches that are coupled to host servers serving specific applications. The GSLB switch receives from site switches operational information regarding host servers within the site switches neighborhood. This operational information includes health check information that is remotely obtained in a distributed manner from remote metric agents at the site switches. When a client program requests a resolution of a host name, the GSLB switch, acting as a proxy of an authoritative DNS, returns one or more ordered IP addresses for the host name. The IP addresses are ordered using metrics, including the health check metric that evaluates these IP addresses based on the health check information communicated to the GSLB switch in a distributed manner by the distributed health check site switches. In one instance, the GSLB switch places the address that is deemed “best” at the top of the list. | 05-13-2010 |
20100235507 | CONNECTION RATE LIMITING FOR SERVER LOAD BALANCING AND TRANSPARENT CACHE SWITCHING - Each service in a computer network may have a connection rate limit. The number of new connections per time period may be limited by using a series of rules. In a specific embodiment of the present invention, a counter is increased each time a server is selected to handle a connection request. For each service, connections coming in are tracked. Therefore, the source of connection-request packets need not be examined. Only the destination service is important. This saves significant time in the examination of the incoming requests. Each service may have its own set of rules to best handle the new traffic for its particular situation. For server load balancing, a reset may be sent to the source address of the new connection request. For transparent cache switching, the connection request may be forwarded to the Internet. | 09-16-2010 |
20110082947 | CONNECTION RATE LIMITING - Each service in a computer network may have a connection rate limit. The number of new connections per time period may be limited by using a series of rules. In a specific embodiment of the present invention, a counter is increased each time a server is selected to handle a connection request. For each service, connections coming in are tracked. Therefore, the source of connection-request packets need not be examined. Only the destination service is important. This saves significant time in the examination of the incoming requests. Each service may have its own set of rules to best handle the new traffic for its particular situation. | 04-07-2011 |
20140025772 | Connection Rate Limiting For Server Load Balancing And Transparent Cache Switching - Each service in a computer network may have a connection rate limit. The number of new connections per time period may be limited by using a series of rules. In a specific embodiment of the present invention, a counter is increased each time a server is selected to handle a connection request. For each service, connections coming in are tracked. Therefore, the source of connection-request packets need not be examined. Only the destination service is important. This saves significant time in the examination of the incoming requests. Each service may have its own set of rules to best handle the new traffic for its particular situation. For server load balancing, a reset may be sent to the source address of the new connection request. For transparent cache switching, the connection request maybe forwarded to the Internet. | 01-23-2014 |
Patent application number | Description | Published |
20100041010 | Method to treat collagenous connective tissue for implant remodeled by host cells into living tissue - The invention relates to a method of treatment of collagenous connective tissue removed from a donor for implant into a recipient which is re-habited or re-colonized by host cells without an immune rejection and inflammatory reaction. After removal from the donor the tissue is trimmed and thereafter soaked in a cold stabilizing solution having a temperature range of 4 to 10 degrees centigrade. The tissue is then soaked at a predetermined temperature in a polyglycol, salt, hydrogen peroxide, and phosphate buffer first solution of predetermined quantities and concentrations and of sufficient ionic strength to permit ground substances to dissociate such that the collagen fibers remain stable. The tissue is then soaked in an alcohol and water solution at a predetermined temperature for a sufficient period of time to remove the residue of the first solution. Following the removal of the residue, the tissue is soaked at a predetermined temperature in a third solution of an anti-inflammatory agent, an anti-thrombic agent, alcohol, and water or sequentially in an anti-inflammatory agent, alcohol, and water solution, and then in an anti-thrombic agent, alcohol and water solution and thereafter stored. | 02-18-2010 |
20110091516 | Muscle-based grafts/implants - The present invention is directed to a composition comprising a matrix suitable for implantation in humans, comprising defatted, shredded, allogeneic human muscle tissue that has been combined with an aqueous carrier and dried in a predetermined shape. Also disclosed is a tissue graft or implant comprising a matrix suitable for implantation in humans, comprising defatted, shredded, allogeneic human muscle tissue that has been combined with an aqueous carrier and dried in a predetermined shape. The composition and/or tissue graft or implant of the invention is usable in combination with seeded cells, a tissue growth factor, and/or a chemotactic gent to attract a desired cell. | 04-21-2011 |
20130149356 | Muscle-based grafts/implants - The present invention is directed to a composition comprising a matrix suitable for implantation in humans, comprising defatted, shredded, allogeneic human muscle tissue that has been combined with an aqueous carrier and dried in a predetermined shape. Also disclosed is a tissue graft or implant comprising a matrix suitable for implantation in humans, comprising defatted, shredded, allogeneic human muscle tissue that has been combined with an aqueous carrier and dried in a predetermined shape. The composition and/or tissue graft or implant of the invention is usable in combination with seeded cells, a tissue growth factor, and/or a chemotactic agent to attract a desired cell. | 06-13-2013 |
20140257516 | Connective-Tissue-Based or Dermal-Tissue-Based Grafts/Implants - The present invention is directed to a composition comprising a matrix suitable for implantation in humans, comprising defatted, shredded, allogeneic human muscle tissue that has been combined with an aqueous carrier and dried in a predetermined shape. Also disclosed is a tissue graft or implant comprising a matrix suitable for implantation in humans, comprising defatted, shredded, allogeneic human muscle tissue that has been combined with an aqueous carrier and dried in a predetermined shape. The composition and/or tissue graft or implant of the invention is usable in combination with seeded cells, a tissue growth factor, and/or a chemotactic gent to attract a desired cell. | 09-11-2014 |
Patent application number | Description | Published |
20090074383 | Video processing system - The present invention is directed to a system for demultiplexing video signals that have been combined using a time division multiplexing approach. The system includes synchronizers, parsers, demultiplexers, and an input buffer. Each demultiplexer within the system includes a header detect module, a slot map module, a frame sync module and a packet accept module. The method includes the steps of receiving an input stream that contains data packets for more than one program channel that have been combined in which packet identification (PID) information is used and a time division multiplexing scheme, such as transport stream multiplexing format (TSMF) is used. The PID and slot location for each packet is analyzed. Based on the PID and slot location a packet is either accepted or rejected. | 03-19-2009 |
20090150923 | Packetization of non-MPEG stream data in systems using advanced multi-stream POD interface - Aspects of the present invention may be found in one or more systems and/or methods to encapsulate or packetize non-MPEG and MPEG data. The encapsulation or packetization allows both the non-MPEG and MPEG data to be utilized by a set-top-box that conforms or complies with the OpenCable™ Advanced Multi-Stream POD Interface Specification and/or the OpenCable™ Multi-Stream CableCARD Interface Specification. In one embodiment, a method of processing video data, by a set-top-box that is communicatively coupled to a POD card, comprises receiving video data from a provider, first packetizing the video data using a first header to generate a first packet, wherein the first header comprises a first indicator. In one embodiment, a system for providing MPEG and non-MPEG video to a subscriber comprises a circuitry and a POD card capable of receiving, processing, and facilitating the display of non-MPEG and MPEG data. | 06-11-2009 |
20090190656 | Television Functionality on a Chip - A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies. | 07-30-2009 |
20090245285 | Method for Data Packet Substitution - A system and method for substituting data packets into a data stream, is provided. In one embodiment, the data stream is a video data stream. The system includes packet buffers, a multiplexer, a packet substitution controller, a direct memory access (DMA) engine and a link list buffer controller. A method is also provided for substituting data packets - containing information of the same or different type—into a video data stream at variable rates using a selection mechanism driven by link list buffer control. | 10-01-2009 |
20100103195 | VIDEO, AUDIO AND GRAPHICS DECODE, COMPOSITE AND DISPLAY SYSTEM - A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. | 04-29-2010 |
20120147974 | Television Functionality on a Chip - A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies. | 06-14-2012 |
20130308927 | APPARATUS AND METHOD OF SEAMLESS SWITCHING BETWEEN A LIVE DTV DECODING AND A PVR PLAYBACK - Methods and apparatus for switching between a live video decoding and a recorded playback in a digital video and recording system. A received video data stream is transmitted to a first-in first-out video decoder buffer without first looping the video data stream through a playback buffer. The video data stream is transmitted from the video decoder buffer to a video decoder. If a “pause” command is received, the video data stream is transmitted to a first-in first-out playback buffer, while continuing to transmit the video data stream to the video decoder buffer. Transmission of the video data stream to the video decoder buffer is halted when the video decoder buffer fills up. The last byte of the video data stream that was transmitted to the video decoder buffer is marked. If a “play” command is received, the video data stored in the video decoder buffer is transmitted to the video decoder. The video data stored in the playback buffer is transmitted to the video decoder buffer starting at a point immediately after the data element that was marked previously. | 11-21-2013 |
20140181985 | Content Specific Data Scrambling - An electronic device may include multiple modules that share access to a common memory. The electronic device may include content access logic that selective allows a module to access target data in the memory. When writing data into the memory, the content access logic may determine an access restriction associated with the write data, where the access restriction specifies one or more modules that can access the write data. The content access logic may scramble the write date using an access key, and configure the access key such that only authorized modules can use the access key when retrieving data from the memory. The content access logic may then store the scrambled data in the memory. | 06-26-2014 |
Patent application number | Description | Published |
20100306556 | METHOD AND SYSTEM FOR RANDOM DATA ACCESS FOR SECURITY APPLICATIONS - A method for securely handling processing of information in a chip may include randomly selecting one of a plurality of data processes based on a random process index. A time interval may be randomly allocated on the chip, for processing the randomly selected one of the plurality of data processes. When the randomly allocated time interval has elapsed, the randomly selected one of the plurality of data processes may be initiated. The randomly selected one of the plurality of data processes may include one or both of accessing data and acquiring the data. Data may be verified by the randomly selected one of the plurality of data processes prior to the processing of the data. The data may be verified utilizing at least one digital signature verification algorithm, such as a Rivest-Shamir-Adelman (RSA) algorithm and/or a secure hash algorithm (SHA-1). | 12-02-2010 |
20110202776 | Storage Device Content Authentication - Systems and methods that support storage device content authentication are provided. A system that verifies storage device content received from a storage device may comprise, for example, a security processor coupled to the storage device. The security processor may be adapted to receive a partitioned storage device region from the storage device. The partitioned storage device region may comprise, for example, regional content and first hashed regional content. The security processor may generate, for example, second hashed regional content by performing a hashing function on the regional content received by the security processor. The security processor may compare, for example, the first hashed regional content to the second hashed regional content. The security processor may verify the regional content received by the security processor if the first hashed regional content is the same as the second hashed regional content. | 08-18-2011 |
20110247076 | METHOD AND SYSTEM FOR RANDOM DATA ACCESS FOR SECURITY APPLICATIONS - A method for securely handling processing of information includes, in a chip, selecting one of a plurality of data processes based on a random index. After a randomly allocated time interval has elapsed, the selected one of the plurality of data processes may be initiated. The selected one of the plurality of data processes may include accessing data and/or acquiring the data. Burstiness of the data may be approximately equal to burstiness of data acquired by at least one of a plurality of clients on the chip. Data may be verified by the selected one of the plurality of data processes prior to the processing of the data. | 10-06-2011 |
20150082337 | PIPELINED ENCRYPTION AND PACKETIZATION OF AUDIO VIDEO DATA - A system for pipelined encryption and packetization of audio video (AV) data may consecutively encrypt a number of AV data units based on a security mechanism, associate the encrypted AV data units with a security header, where the security header is generated before the AV data units are encrypted, and the security header includes information related to the security mechanism, generate network packets for transporting the encrypted AV data units and the associated security header based at least in part on an order in which the AV data units are encrypted, where one or more of the network packets is generated contemporaneous with encrypting one or more of the AV data units, and provide the network packets for transport to a client device as the packets are generated, where the AV data units are encrypted and the network packets are generated without accessing memory external to the system. | 03-19-2015 |
Patent application number | Description | Published |
20100152893 | Method and apparatus for on-demand kiosk fulfillment with origination, billing, and management via telecommunications network - An automated method of purchasing kiosk items, where a toll call from a variety of typically mobile appliances (i.e. cell phone, PDA, tablet PC, personal desktop or laptop computer, etc.) activates an apparatus that causes the automated kiosk to fulfill demanded items upon successful validation and billing via an interface to a telecommunications network. A mobile phone can therefore be billed by dialing a “1-900” type toll number and specify the desired product via touch tone commands, or by similarly “texting” the order to a designated telecommunications recipient. Furthermore, the apparatus includes a means to provide maintenance and diagnostics and services so as to minimize operating costs of the kiosk system, along with necessary management services such as inventory control. The kiosk can be interfaced with the telecommunications network in a variety of ways, such as, but not limited to POTS modem for twisted pair copper, DSL modem for twisted pair copper, Ethernet controller for CAT-5, etc., and includes a plurality of sensors and actuators to execute the variety of functionalities specified (i.e., motors to deploy product, temperature sensor to qualify product, image capture device to validate delivery of product, etc.). The apparatus may include a central server to interact with the end user and to deliver network commands (e.g., present end-user with options, accept order from end-user, identify inventory, deploy particular product, query current kiosk status, etc.), as well as report product description and billing data back to the mobile appliance's telecommunication network. | 06-17-2010 |
Patent application number | Description | Published |
20090061650 | SACRIFICIAL NITRIDE AND GATE REPLACEMENT - Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved. | 03-05-2009 |
20090101963 | SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS - Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes. | 04-23-2009 |
20100203694 | METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES - Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask. | 08-12-2010 |
20110237060 | SACRIFICIAL NITRIDE AND GATE REPLACEMENT - Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved. | 09-29-2011 |
20130277733 | FLASH MEMORY DEVICES AND METHODS FOR FABRICATING SAME - Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material. | 10-24-2013 |
20140024190 | DUAL STORAGE NODE MEMORY - An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements. | 01-23-2014 |
Patent application number | Description | Published |
20100165990 | SYSTEMS AND METHODS FOR EFFICIENT MULTICAST HANDLING - A network device constructs a notification corresponding to a received multicast data unit, where the notification includes administrative data associated with the multicast data unit that does not include a payload of the multicast data unit. The network device replicates the notification at least three different processing elements at different locations in a processing path of the network device to produce multiple replicated data items and produces a copy of the multicast data unit for each of replicated notifications. The network device forwards each copy of the multicast data unit towards a multicast destination. | 07-01-2010 |
20100246584 | MAINTAINING PACKET ORDER USING HASH-BASED LINKED-LIST QUEUES - Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue. | 09-30-2010 |
20110264822 | FILTERING AND ROUTE LOOKUP IN A SWITCHING DEVICE - Methods and devices for processing packets are provided. The processing device may Include an input interface for receiving data units containing header information of respective packets; a first module configurable to perform packet filtering based on the received data units; a second module configurable to perform traffic analysis based on the received data units; a third module configurable to perform load balancing based on the received data units; and a fourth module configurable to perform route lookups based on the received data | 10-27-2011 |
20120027019 | MAINTAINING PACKET ORDER USING HASH-BASED LINKED-LIST QUEUES - Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue. | 02-02-2012 |
20120263178 | SYSTEMS AND METHODS FOR EFFICIENT MULTICAST HANDLING - A network device constructs a notification corresponding to a received multicast data unit, where the notification includes administrative data associated with the multicast data unit that does not include a payload of the multicast data unit. The network device replicates the notification at at least three different processing elements at different locations in a processing path of the network device to produce multiple replicated data items and produces a copy of the multicast data unit for each of replicated notifications. The network device forwards each copy of the multicast data unit towards a multicast destination. | 10-18-2012 |
20120275459 | PROCESSING PACKETS BY A NETWORK DEVICE - A method and apparatus for performing a lookup in a switching device of a packet switched network where the lookup includes a plurality of distinct operations each of which returns a result that includes a pointer to a next operation in a sequence of operations for the lookup. The method includes determining a first lookup operation to be executed, executing the first lookup operation including returning a result and determining if the result includes a pointer to another lookup operation in the sequence of operations. If the result includes a pointer to another lookup operation, the lookup operation indicated by the result is executed. Else, the lookup is terminated. | 11-01-2012 |
20120297083 | FILTERING AND ROUTE LOOKUP IN A SWITCHING DEVICE - Methods and devices for processing packets are provided. The processing device may Include an input interface for receiving data units containing header information of respective packets; a first module configurable to perform packet filtering based on the received data units; a second module configurable to perform traffic analysis based on the received data units; a third module configurable to perform load balancing based on the received data units; and a fourth module configurable to perform route lookups based on the received data units. | 11-22-2012 |
20130138758 | Efficient data transfer between servers and remote peripherals - Methods and apparatus are provided for transferring data between servers and a remote entity having multiple peripherals. Multiple servers are connected to a remote entity over an Remote Direct Memory Access capable network. The remote entity includes peripherals such as network interface cards (NICs) and host bus adapters (HBAs). Server descriptor rings and descriptors are provided to allow efficient and effective communication between the servers and the remote entity. | 05-30-2013 |
20130308644 | FILTERING AND ROUTE LOOKUP IN A SWITCHING DEVICE - Methods and devices for processing packets are provided. The processing device may Include an input interface for receiving data units containing header information of respective packets; a first module configurable to perform packet filtering based on the received data units; a second module configurable to perform traffic analysis based on the received data units; a third module configurable to perform load balancing based on the received data units; and a fourth module configurable to perform route lookups based on the received data | 11-21-2013 |
20140347995 | PROCESSING PACKETS BY A NETWORK DEVICE - A method and apparatus for performing a lookup in a switching device of a packet switched network where the lookup includes a plurality of distinct operations each of which returns a result that includes a pointer to a next operation in a sequence of operations for the lookup. The method includes determining a first lookup operation to be executed, executing the first lookup operation including returning a result and determining if the result includes a pointer to another lookup operation in the sequence of operations. If the result includes a pointer to another lookup operation, the lookup operation indicated by the result is executed. Else, the lookup is terminated. | 11-27-2014 |
Patent application number | Description | Published |
20100203056 | ANTI-PD-L1 ANTIBODIES AND THEIR USE TO ENHANCE T-CELL FUNCTION - The present application relates to anti-PD-L1 antibodies, nucleic acid encoding the same, therapeutic compositions thereof, and their use enhance T-cell function to upregulate cell-mediated immune responses and for the treatment of T cell dysfunctional disorders, including infection (e.g., acute and chronic) and tumor immunity. | 08-12-2010 |
20130045200 | METHODS OF USING ANTI-PD-L1 ANTIBODIES AND THEIR USE TO TREAT INFECTION RESULTING FROM T-CELL DYSFUNCTION - The present application relates to methods of using anti-PD-L1 antibodies to enhance T-cell function to upregulate cell-mediated immune responses and for the treatment of T cell dysfunctional disorders, including infection (e.g., acute and chronic) and tumor immunity. | 02-21-2013 |
20130045201 | METHODS OF USING ANTI-PD-L1 ANTIBODIES AND THEIR USE TO ENHANCE T-CELL FUNCTION TO TREAT TUMOR IMMUNITY - The present application relates to methods of using anti-PD-L1 antibodies to enhance T-cell function to upregulate cell-mediated immune responses and for the treatment of T cell dysfunctional disorders, including infection (e.g., acute and chronic) and tumor immunity. | 02-21-2013 |
20130045202 | ANTI-PD-L1 ANTIBODIES AND ARTICLES OF MANUFACTURE - The present application relates to anti-PD-L1 antibodies, which have therapeutic use to enhance T-cell function to upregulate cell-mediated immune responses and for the treatment of T cell dysfunctional disorders, including infection (e.g., acute and chronic) and tumor immunity. | 02-21-2013 |
20140065135 | METHODS OF USING ANTI-PD-L1 ANTIBODIES AND THEIR USE TO ENHANCE T-CELL FUNCTION TO TREAT TUMOR IMMUNITY - The present application relates to methods of using anti-PD-L1 antibodies to enhance T-cell function to upregulate cell-mediated immune responses and for the treatment of T cell dysfunctional disorders, including infection (e.g., acute and chronic) and tumor immunity. | 03-06-2014 |
Patent application number | Description | Published |
20090191569 | Mammalian Cytokines; Related Reagents - Purified genes encoding a cytokine or composite cytokine from a mammal, reagents related thereto including purified proteins, specific antibodies, and nucleic acids encoding these molecules are provided. Methods of using said reagents and diagnostic kits are also provided. | 07-30-2009 |
20110136172 | MAMMALIAN CYTOKINES; RELATED REAGENTS - Purified genes encoding a cytokine or composite cytokine from a mammal, reagents related thereto including purified proteins, specific antibodies, and nucleic acids encoding these molecules are provided. Methods of using said reagents and diagnostic kits are also provided. | 06-09-2011 |
20120115164 | MAMMALIAN CYTOKINES; RELATED REAGENTS - Purified genes encoding a cytokine or composite cytokine from a mammal, reagents related thereto including purified proteins, specific antibodies, and nucleic acids encoding these molecules are provided. Methods of using said reagents and diagnostic kits are also provided. | 05-10-2012 |
20140170658 | MAMMALIAN CYTOKINES; RELATED REAGENTS - Purified genes encoding a cytokine or composite cytokine from a mammal, reagents related thereto including purified proteins, specific antibodies, and nucleic acids encoding these molecules are provided. Methods of using said reagents and diagnostic kits are also provided. | 06-19-2014 |
Patent application number | Description | Published |
20090212112 | BARCODE DETECTION BASED ON MORPHOLOGICAL OPERATIONS - This disclosure describes techniques for detecting a barcode within an image. An image processor may, for example, process an image to detect regions within the image that may be barcodes. The image processor may identify regions of the image that exhibit a high concentration of edges and a high concentration of pixels with low optical intensity co-instantaneously as potential barcodes. The image processor may identify the regions using a number of morphological operations. The image processor may then determine whether the identified regions are actually barcodes by verifying whether the region have unique barcode features. The barcode detection techniques described in this disclosure may be independent of barcode size, location and orientation within the image. Moreover, the use of morphological operations results in faster and more computationally efficient barcode detection, as well as lower computational complexity. | 08-27-2009 |
20090212113 | IMAGE CAPTURE DEVICE WITH INTEGRATED BARCODE SCANNING - This disclosure describes barcode scanning techniques for an image capture device. The image capture device may automatically detect a barcode within an image while the image capture device is operating in a non-barcode image capture mode, such a default image capture mode. In one aspect, the detection of the barcode within the image may be based on a combination of identified edges and low intensity regions within the image. The image capture device may configure, based on the detection of the barcode, one or more image capture properties associated with the image capture device to improve a quality at which the images are captured. The image capture device captures the image in accordance with the configured image capture properties. The techniques may effectively provide a universal and integrated front-end for producing improved quality images of barcodes without requiring significant interaction with a user via a complicated user interface. | 08-27-2009 |
20100254617 | APPARATUS AND METHOD TO ROTATE AN IMAGE - Image processing systems and methods are disclosed. In a particular embodiment, a method is disclosed that includes receiving image data of an image. The image data includes a plurality of image blocks. The method further includes calculating a first differential DC value during a rotation operation of the image by comparing a first DC coefficient value of a first block of a first row of the image to a second DC coefficient value of a first block of a second row of the image. The method further includes storing the first differential DC value in a memory prior to completing the rotation operation. | 10-07-2010 |
20110242342 | COMBINING DATA FROM MULTIPLE IMAGE SENSORS - A method of combining data from multiple sensors is disclosed. The method includes providing a common control signal to multiple image sensors to be synchronized. The method further includes receiving a first data line from a first image sensor of the multiple image sensors, receiving a second data line from a second image sensor of the multiple image sensors, and combining the first data line and the second data line to generate a synchronized data line. | 10-06-2011 |
20110242355 | COMBINING DATA FROM MULTIPLE IMAGE SENSORS - A method of combining data from multiple sensors is disclosed. The method includes providing a common control signal to multiple image sensors. Each of the multiple image sensors is responsive to the common control signal to generate image data. The method also includes receiving synchronized data output from each of the multiple image sensors, combining the synchronized data output from each of the multiple image sensors to generate a synchronized data line, and providing the synchronized data line to an image processor via a single camera input of the image processor. | 10-06-2011 |
20110242356 | COMBINING DATA FROM MULTIPLE IMAGE SENSORS - A method of combining data from multiple sensors is disclosed. The method includes providing a common control signal to multiple image sensors. Each of the multiple image sensors is responsive to the common control signal to generate image data. The method also includes receiving synchronized data output from each of the multiple image sensors. | 10-06-2011 |
20120081519 | COMBINING DATA FROM MULTIPLE IMAGE SENSORS - A method of combining data from multiple sensors is disclosed. The method includes receiving lines of image data at an image processor having an input for a single camera. Each line of the image data includes first line data from a first image captured by a first camera and second line data from a second image captured by a second camera. The method also includes generating an output frame having a first section corresponding to line data of the first image and having a second section corresponding to line data of the second image. The first section and the second section are configured to be used to generate a three-dimensional (3D) image format or a 3D video format. | 04-05-2012 |
20120120256 | PARALLEL IMAGE PROCESSING USING MULTIPLE PROCESSORS - An electronic device for parallel image processing using multiple processors is disclosed. The electronic device includes multiple image sensors for providing image data. The electronic device also includes multiple processors for processing segmented image data to produce processed segmented image data. Each processor is dedicated to one of the image sensors. A multiple processor interface is also included. The multiple processor interface maps the image data to the processors, segments the image data to produce the segmented image data and synchronizes the segmented image data to processor clock rates. | 05-17-2012 |
20120300034 | INTERACTIVE USER INTERFACE FOR STEREOSCOPIC EFFECT ADJUSTMENT - Present embodiments contemplate systems, apparatus, and methods to determine a user's preference for depicting a stereoscopic effect. Particularly, certain of the embodiments contemplate receiving user input while displaying a stereoscopic video sequence. The user's preferences may be determined based upon the input. These preferences may then be applied to future stereoscopic depictions. | 11-29-2012 |
20140254711 | EFFICIENT N-FACTORIAL DIFFERENTIAL SIGNALING TERMINATION NETWORK - A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements. | 09-11-2014 |
20140254732 | TRANSCODING METHOD FOR MULTI-WIRE SIGNALING THAT EMBEDS CLOCK INFORMATION IN TRANSITION OF SIGNAL STATE - A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires. | 09-11-2014 |
20140254733 | CIRCUIT TO RECOVER A CLOCK SIGNAL FROM MULTIPLE WIRE DATA SIGNALS THAT CHANGES STATE EVERY STATE CYCLE AND IS IMMUNE TO DATA INTER-LANE SKEW AS WELL AS DATA STATE TRANSITION GLITCHES - A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions while compensating for skew in the different data lines, and masking data state transition glitches. | 09-11-2014 |
20140270005 | SHARING HARDWARE RESOURCES BETWEEN D-PHY AND N-FACTORIAL TERMINATION NETWORKS - A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding. | 09-18-2014 |
20140270026 | MULTI-WIRE SINGLE-ENDED PUSH-PULL LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols. | 09-18-2014 |
20140286466 | MULTI-WIRE OPEN-DRAIN LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING - A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions. | 09-25-2014 |
20140372642 | CAMERA CONTROL INTERFACE EXTENSION BUS - System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols. | 12-18-2014 |
20140372643 | CAMERA CONTROL INTERFACE EXTENSION BUS - System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols. | 12-18-2014 |
20140372644 | CAMERA CONTROL INTERFACE EXTENSION BUS - System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. The bus has a first line and a second line, a first set of devices coupled to the bus and a second set of devices coupled to the bus. A method of operating the bus includes configuring the first set of devices to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation, and configuring the second set of devices to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation. | 12-18-2014 |
Patent application number | Description | Published |
20100262299 | SYSTEM AND METHOD FOR USING RAMPED SETPOINT TEMPERATURE VARIATION WITH NETWORKED THERMOSTATS TO IMPROVE EFFICIENCY - The invention comprises systems and methods for ramping setpoints on thermostats controlling HVAC systems. At least one thermostat is located inside a structure and is used to control an HVAC system in the structure. At least one remote processor is in communication with said thermostat and at least one database stores data reported by the thermostat. At least one processor compares the outside temperature at least one location and at least one point in time to information reported to the remote processor from the thermostat. The remote processor ramps the setpoint on the thermostat so as to reduce the average spread between inside temperature and outside temperature in order to reduce energy consumption with affecting comfort. The remote processor takes into account the effect of weather conditions and occupant preferences in determining whether and when to ramp setpoints. | 10-14-2010 |
20100308119 | SYSTEM, METHOD AND APPARATUS FOR IDENTIFYING MANUAL INPUTS TO AND ADAPTIVE PROGRAMMING OF A THERMOSTAT - Systems and methods are disclosed for incorporating manual changes to the setpoint for a thermostatic controller into long-term programming of the thermostatic controller. For example, one or more of the exemplary systems compares the actual setpoint at a given time for the thermostatic controller to an expected setpoint for the thermostatic controller in light of the scheduled programming. A determination is then made as to whether the actual setpoint and the expected setpoint are the same or different. Furthermore, a manual change to the actual setpoint for the thermostatic controller is compared to previously recorded setpoint data for the thermostatic controller. At least one rule is then applied for the interpretation of the manual change in light of the previously recorded setpoint data. | 12-09-2010 |
20100318227 | SYSTEM, METHOD AND APPARATUS FOR JUST-IN-TIME CONDITIONING USING A THERMOSTAT - Systems and methods for reducing the cycling time of a climate control system. For example, one or more of the exemplary systems can receive from a database a target time at which a structure is desired to reach a target temperature. In addition, the system acquires the temperature inside the structure and the temperature outside the structure at a time prior to said target time. The systems use a thermal characteristic of the structure and a performance characteristic of the climate control system, to determine the appropriate time prior to the target time at which the climate control system should turn on based at least in part on the structure, the climate control system, the inside temperature and the outside temperature. The systems then set a setpoint on a thermostatic controller to control the climate control system. | 12-16-2010 |
20110307103 | SYSTEM AND METHOD FOR USING RAMPED SETPOINT TEMPERATURE VARIATION WITH NETWORKED THERMOSTATS TO IMPROVE EFFICIENCY - The invention comprises systems and methods for ramping setpoints on thermostats controlling HVAC systems. At least one thermostat is located inside a structure and is used to control an HVAC system in the structure. At least one remote processor is in communication with said thermostat and at least one database stores data reported by the thermostat. At least one processor compares the outside temperature at least one location and at least one point in time to information reported to the remote processor from the thermostat. The remote processor ramps the setpoint on the thermostat so as to reduce the average spread between inside temperature and outside temperature in order to reduce energy consumption with affecting comfort. The remote processor takes into account the effect of weather conditions and occupant preferences in determining whether and when to ramp setpoints. | 12-15-2011 |
20130310989 | REMOTE MANAGEMENT OF COMMUNICATING THERMOSTAT TO ACHIEVE JUST IN TIME CONDITIONING - Systems and methods for reducing the cycling time of a climate control system. For example, one or more of the exemplary systems can receive from a database a target time at which a structure is desired to reach a target temperature. In addition, the system acquires the temperature inside the structure and the temperature outside the structure at a time prior to said target time. The systems use a thermal characteristic of the structure and a performance characteristic of the climate control system, to determine the appropriate time prior to the target time at which the climate control system should turn on based at least in part on the structure, the climate control system, the inside temperature and the outside temperature. The systems then set a setpoint on a thermostatic controller to control the climate control system. | 11-21-2013 |
20140188290 | SYSTEM, METHOD AND APPARATUS FOR IDENTIFYING MANUAL INPUTS TO AND ADAPTIVE PROGRAMMING OF A THERMOSTAT - Systems and methods are disclosed for incorporating manual changes to the setpoint for a thermostatic controller into long-term programming of the thermostatic controller. For example, one or more of the exemplary systems compares the actual setpoint at a given time for the thermostatic controller to an expected setpoint for the thermostatic controller in light of the scheduled programming. A determination is then made as to whether the actual setpoint and the expected setpoint are the same or different. Furthermore, a manual change to the actual setpoint for the thermostatic controller is compared to previously recorded setpoint data for the thermostatic controller. At least one rule is then applied for the interpretation of the manual change in light of the previously recorded setpoint data. | 07-03-2014 |
Patent application number | Description | Published |
20100156997 | DROP GENERATING APPARATUS - A drop generator having a via structure configured for electrical and fluidic interconnection. The via structure includes an electrically conductive layer and an electrically insulating layer disposed on the electrically conductive layer. | 06-24-2010 |
20100159193 | COMBINED ELECTRICAL AND FLUIDIC INTERCONNECT VIA STRUCTURE - A via structure configured for electrical and fluidic interconnection, and including an electrically conductive layer and an electrically insulating layer disposed on the electrically conductive layer. | 06-24-2010 |
20100206302 | Rotational Trough Reflector Array For Solar-Electricity Generation - A rotational trough reflector solar-electricity generation device includes a trough reflector that rotates around a substantially vertical axis. A strip-type photovoltaic (PV) device, or other solar-energy collection element, is fixedly mounted along the focal line of the trough reflector. A tracking system rotates the trough reflector such that the trough reflector is aligned generally parallel to the incident sunlight (e.g., in a generally east-west direction at sunrise, turning to generally north-south at noon, and turning generally west-east at sunset). A disc-shaped support structure is used to distribute the reflector's weight over a larger area and to minimize the tracking system motor size. Multiple trough reflectors are mounted on the disc-shaped support to maximize power generation. Flat mirrors are disposed at the end of the troughs to increase power in “hot” PV sections that are connected in series. | 08-19-2010 |
20100206356 | Rotational Trough Reflector Array For Solar-Electricity Generation - A rotational trough reflector solar-electricity generation device includes a trough reflector that rotates around a substantially vertical axis. A strip-type photovoltaic (PV) device is fixedly mounted along the focal line of the trough reflector. A tracking system rotates the trough reflector such that the trough reflector is aligned generally parallel to the incident sunlight (e.g., in a generally east-west direction at sunrise, turning to generally north-south at noon, and turning generally west-east at sunset). A disc-shaped support structure is used to distribute the reflector's weight over a larger area and to minimize the tracking system motor size. Multiple trough reflectors are mounted on the disc-shaped support to maximize power generation. | 08-19-2010 |
20100206357 | Two-Part Solar Energy Collection System With Replaceable Solar Collector Component - A two-part solar energy collection system for installation on a planar support surface (e.g., a rooftop) includes a permanent positioning component including a base structure and a replaceable solar collector component including solar energy collection elements fixedly mounted on a support frame. Each collection element includes an optical element arranged to focus solar radiation onto a focal line, and a linearly-arranged solar energy collector (e.g., PV cells) fixedly maintained on the focal line. The replaceable solar collector component is secured to a rotating platform of the base structure such that the focal lines of the solar energy collection elements are maintained in a plane that is substantially parallel to the support surface, and the rotating platform and replaceable solar collector component are collectively pivoted by a positioning system around a rotational axis to align the PV cells) parallel to the received sunlight beams. | 08-19-2010 |
20100206379 | Rotational Trough Reflector Array With Solid Optical Element For Solar-Electricity Generation - A rotational trough reflector solar-electricity generation device includes a trough reflector that rotates around a substantially vertical axis and includes a solid optical element having a linear parabolic convex surface that serves as a base for automatically positioning a mirror to focus sunlight onto a focal line, and a flat aperture surface that serves to support a strip-type photovoltaic (PV) receiver on the focal line. A tracking system rotates the trough reflector such that the trough reflector is aligned generally parallel to the incident sunlight (e.g., in a generally east-west direction at sunrise, turning to generally north-south at noon, and turning generally west-east at sunset). A disc-shaped support structure is used to distribute the reflector's weight over a larger area and to minimize the tracking system motor size. Multiple trough reflectors are mounted on the disc-shaped support to maximize power generation. | 08-19-2010 |
20110100418 | Solid Linear Solar Concentrator Optical System With Micro-Faceted Mirror Array - A concentrating solar collector includes a solid optical structure a flat front surface, and PV cells and a micro-faceted mirror array disposed on the opposing rear surface. The micro-faceted mirrors are arranged in a sawtooth arrangement to reflect sunlight toward the front surface at angles that produces total internal reflection (TIR) and redirection of the sunlight onto the PV cells. The micro-faceted mirror array reflects sunlight onto the PV cells in an extended focus region of concentrated light that has a substantially uniform or homogeneous irradiance distribution pattern. The optical structure is a solid dielectric sheet either processed to include micro-faceted surfaces with reflective material formed thereon, or having a dielectric film including the micro-faceted mirror array adhered thereon. In one embodiment, three PV cells and four micro-faceted mirror arrays are disposed in an interleaved pattern with two side mirrors are disposed on side edges of the optical structure. | 05-05-2011 |
20110259397 | Rotational Trough Reflector Array For Solar-Electricity Generation - A rotational trough reflector solar-electricity generation device includes a trough reflector that rotates around a substantially vertical axis. A strip-type photovoltaic (PV) device is fixedly mounted along the focal line of the trough reflector. A tracking system rotates the trough reflector such that the trough reflector is aligned generally parallel to the incident sunlight (e.g., in a generally east-west direction at sunrise, turning to generally north-south at noon, and turning generally west-east at sunset). A disc-shaped support structure is used to distribute the reflector's weight over a larger area and to minimize the tracking system motor size. Multiple trough reflectors are mounted on the disc-shaped support to maximize power generation. | 10-27-2011 |
20120325313 | Solar-Tower System With High-Focus-Accuracy Mirror Array - A solar-tower system includes a raised solar receiver disposed on a tower and a mirror array including multiple flat mirrors for reflecting sunlight onto the raised receiver. The mirror array is disposed on a carousel-type platform that is rotatable around a vertical axis, and the raised receiver is maintained at a substantially fixed position relative to the mirror array for all rotational positions of the platform. A solar azimuth tracking controller controls the platform's rotational position to track the sun's azimuth angle such that sunlight shines on the mirror array from a fixed apparent azimuth angle at all times during daylight hours. Each flat mirror pivots around a corresponding unique axis, and a solar elevation tracking controller individually controls each mirror's pivot position to track the sun's elevation angle such that sunlight is accurately reflected onto the raised solar receiver at all times during daylight hours. | 12-27-2012 |
20120325314 | Solar Power Collection Using High-Focus-Accuracy Mirror Array - A method for harvesting solar power by concentrating sunlight onto a raised solar receiver disposed on a tower. The method involves rotating a mirror array made up of multiple flat mirrors as a unit around a vertical axis such that sunlight shines on the mirror array from a fixed apparent azimuth angle at all times during daylight hours, and controlling each mirror's pivot position to track the sun's elevation angle such that sunlight is accurately reflected onto the raised solar receiver at all times during daylight hours. In one embodiment the mirror array is disposed on a roundabout-type platform whose rotational position is controlled to track the sun's azimuth angle and the raised receiver is maintained at a substantially fixed position relative to the mirror array for all rotational positions of the platform. | 12-27-2012 |
20130047977 | Carousel Heliostat Having Louvered Horizontal Mirrors For Solar Tower Systems - A low profile heliostat with elongated louvered mirror segments is provided. Its envelope of revolution has the shape of a flat disc to enable heliostat fields with very high ground coverage ratio. The heliostat's disc-shaped footprint rotates around a substantially vertical axis (akin to a carousel). The short dimension of the mirror segments is drastically shorter than the disc's diameter. Embodiments are described in which the motion relies on two concentric rings, which are individually rotated around a vertical axis. The lower ring acts as a platform providing mainly azimuth tracking, carrying the upper ring. The differential rotation between the upper ring and the lower ring is translated into a rotation of the mirror segments around a second, perpendicular, axis and used for elevation tracking. Disc-shaped heliostat with D-shaped cut-offs are described, to facilitate the required maintenance access even in highly dense heliostat fields. | 02-28-2013 |
20130312412 | Collapsible Solar-Thermal Concentrator For Renewable, Sustainable Expeditionary Power Generator System - A solar-thermal concentrator for a expeditionary power generator system including a portable power plant that utilizes a hybridized solar/fuel Stirling engine to supply electric power in an expeditionary setting. The concentrator includes a collapsible dish assembly that is pivotably and tiltably mounted on a portable base assembly, where the dish assembly includes a lightweight frame including a central mounting structure and multiple truss-like radial arms that are rigidly connected to and extend radially from the central mounting structure, and a reflector panel assembly including multiple flat, fan-shaped reflector panels that are secured to the frame and disposed in a semi-circular pattern. Each reflector panel includes multiple reflectors that collectively form a substantially flat Fresnelized reflective surface that redirects incident sunlight into a focal region. The power plant is maintained in the focal region by a support structure that extends extending perpendicular to the flat reflective surface. | 11-28-2013 |
Patent application number | Description | Published |
20090026441 | Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 01-29-2009 |
20090026442 | Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 01-29-2009 |
20090112520 | SELF-AWARE SEMICONDUCTOR EQUIPMENT - The present invention provides methods and apparatus for predictive maintenance of semiconductor process equipment. In some embodiments, a method for performing predictive maintenance on semiconductor processing equipment includes performing at least one self-diagnostic test on the semiconductor processing equipment with no substrate present in the equipment; comparing a result of the at least one self diagnostic test to at least one baseline characterization of the equipment; and determining whether equipment maintenance is required based upon the comparison. | 04-30-2009 |
20090156012 | METHOD FOR FABRICATING LOW K DIELECTRIC DUAL DAMASCENE STRUCTURES - Methods for forming dual damascene structures in low-k dielectric materials that facilitate reducing photoresist poison issues are provided herein. In some embodiments, such methods may include plasma etching a via through a first mask layer into a low-k dielectric material disposed on a substrate. The first mask layer may then be removed using a process including exposing the first mask layer to a first plasma comprising an oxygen containing gas and at least one of a dilutant gas or a passivation gas, and subsequently exposing the first mask layer to a second plasma comprising an oxygen containing gas and formed using one of either plasma bias power or plasma source power. An anti-reflective coating may then be deposited into the via and atop the low-k dielectric material. A trench may then be plasma etched through a second mask layer formed atop the anti-reflective coating into the low-k dielectric material. | 06-18-2009 |
20100159641 | Memory cell formation using ion implant isolated conductive metal oxide - Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO | 06-24-2010 |
20100159688 | Device fabrication - Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes. | 06-24-2010 |
20100265762 | Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include anon-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 10-21-2010 |
20110133147 | Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 06-09-2011 |
20110155990 | Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 06-30-2011 |
20110229734 | Immersion platinum plating solution - A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces. | 09-22-2011 |
20110315943 | Memory Device Using A Dual Layer Conductive Metal Oxide Structure - Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below un-etched conductive metal oxide layer(s), forming the un-etched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO | 12-29-2011 |
20110315948 | Memory Device Using Ion Implant Isolated Conductive Metal Oxide - Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO | 12-29-2011 |
20120012897 | Vertically Fabricated BEOL Non-Volatile Two-Terminal Cross-Trench Memory Array with Two-Terminal Memory Elements and Method of Fabricating the Same - A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required. | 01-19-2012 |
20120292585 | CONTINUOUS PLANE OF THIN-FILM MATERIALS FOR A TWO-TERMINAL CROSS-POINT MEMORY - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 11-22-2012 |
20120315503 | IMMERSION PLATINUM PLATING SOLUTION - A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces. | 12-13-2012 |
20130059436 | DEVICE FABRICATION - Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes. | 03-07-2013 |
20140087073 | EQUIPMENT AND METHOD OF MANUFACTURING FOR LIQUID PROCESSING IN A CONTROLLED ATMOSPHERIC AMBIENT - In various exemplary embodiments, a system and related method for processing substrates is provided. In one embodiment, a substrate processing system is provided that includes a substrate load module, a plurality of facilities modules, a plurality of process chambers, a substrate transfer module, at least one transfer gate to provide a contamination barrier between various ones of adjacent modules, and at least one gas impermeable shell to provide a controlled atmosphere within the substrate processing system. | 03-27-2014 |
Patent application number | Description | Published |
20110006708 | INTERLEAVING MULTI-ENERGY X-RAY ENERGY OPERATION OF A STANDING WAVE LINEAR ACCELERATOR USING ELECTRONIC SWITCHES - The disclosure relates to systems and methods for fast-switching operating of a standing wave linear accelerator (LINAC) for use in generating x-rays of at least two different energy ranges with advantageously low heating of electronic switches. In certain embodiments, the heating of electronic switches during a fast-switching operation of the LINAC can be kept advantageously low through the controlled, timed activation of multiple electronic switches located in respective side cavities of the standing wave LINAC, or through the use of a modified a side cavity that includes an electronic switch. | 01-13-2011 |
20110216886 | Interleaving Multi-Energy X-Ray Energy Operation Of A Standing Wave Linear Accelerator - The disclosure relates to systems and methods for interleaving operation of a standing wave linear accelerator (LINAC) for use in providing electrons of at least two different energy ranges, which can be contacted with x-ray targets to generate x-rays of at least two different energy ranges. The LINAC can be operated to output electrons at different energies by varying the power of the electromagnetic wave input to the LINAC, or by using a detunable side cavity which includes an activatable window. | 09-08-2011 |
20120081041 | TRAVELING WAVE LINEAR ACCELERATOR BASED X-RAY SOURCE USING PULSE WIDTH TO MODULATE PULSE-TO-PULSE DOSAGE - Provided herein are systems and methods for operating a traveling wave linear accelerator to generate stable electron beams at two or more different intensities by varying the number of electrons injected into the accelerator structure during each pulse by varying the width of the beam pulse, i.e., pulse width. | 04-05-2012 |
20120081042 | TRAVELING WAVE LINEAR ACCELERATOR BASED X-RAY SOURCE USING CURRENT TO MODULATE PULSE-TO-PULSE DOSAGE - Provided herein are systems and methods for operating a traveling wave linear accelerator to generate stable electron beams at two or more different intensities by varying the number of electrons injected into the accelerator structure during each pulse by varying the electron beam current applied to an electron gun. | 04-05-2012 |
20120294422 | SYSTEMS AND METHODS FOR CARGO SCANNING AND RADIOTHERAPY USING A TRAVELING WAVE LINEAR ACCELERATOR BASED X-RAY SOURCE USING CURRENT TO MODULATE PULSE-TO-PULSE DOSAGE - Provided herein are systems and methods for operating a traveling wave linear accelerator to generate stable electron beams at two or more different intensities by varying the number of electrons injected into the accelerator structure during each pulse by varying the electron beam current applied to an electron gun. The electron beams may be used to generate x-rays having selected doses and energies, which may be used for cargo scanning or radiotherapy applications. | 11-22-2012 |
20120294423 | SYSTEMS AND METHODS FOR CARGO SCANNING AND RADIOTHERAPY USING A TRAVELING WAVE LINEAR ACCELERATOR BASED X-RAY SOURCE USING PULSE WIDTH TO MODULATE PULSE-TO-PULSE DOSAGE - Provided herein are systems and methods for operating a traveling wave linear accelerator to generate stable electron beams at two or more different intensities by varying the number of electrons injected into the accelerator structure during each pulse by varying the width of the beam pulse, i.e., pulse width. The electron beams may be used to generate x-rays having selected doses and energies, which may be used for cargo scanning or radiotherapy applications. | 11-22-2012 |
20120313555 | INTERLEAVING MULTI-ENERGY X-RAY ENERGY OPERATION OF A STANDING WAVE LINEAR ACCELERATOR USING ELECTRONIC SWITCHES - The disclosure relates to systems and methods for fast-switching operating of a standing wave linear accelerator (LINAC) for use in generating x-rays of at least two different energy ranges with advantageously low heating of electronic switches. In certain embodiments, the heating of electronic switches during a fast-switching operation of the LINAC can be kept advantageously low through the controlled, timed activation of multiple electronic switches located in respective side cavities of the standing wave LINAC, or through the use of a modified a side cavity that includes an electronic switch. | 12-13-2012 |
20130063052 | INTERLEAVING MULTI-ENERGY X-RAY ENERGY OPERATION OF A STANDING WAVE LINEAR ACCELERATOR - The disclosure relates to systems and methods for interleaving operation of a standing wave linear accelerator (LINAC) for use in providing electrons of at least two different energy ranges, which can be contacted with x-ray targets to generate x-rays of at least two different energy ranges. The LINAC can be operated to output electrons at different energies by varying the power of the electromagnetic wave input to the LINAC, or by using a detunable side cavity which includes an activatable window. | 03-14-2013 |
Patent application number | Description | Published |
20110211443 | NETWORK SWITCH WITH BY-PASS TAP - A network switch apparatus includes a first network port, a second network port, a first inline port, a second inline port, wherein the first and second inline ports are for communication with a pass-through device, a packet switch, and a by-pass device configured to operate in a first mode of operation, wherein in the first mode of operation, the by-pass device is configured to pass a first packet received at the first network port to the packet switch. The by-pass device is configured to switch from the first mode of operation to a second mode of operation upon an occurrence of a condition, and wherein in the second mode of operation, the by-pass device is configured to transmit a second packet received at the first network port to the second network port without passing the second packet to the packet switch. | 09-01-2011 |
20110259894 | APPARATUS AND METHOD FOR CONTAINING EDIBLE ITEMS - An apparatus for containing one or more edible items includes a container having a base and a wall, a first thermal element, and a securing mechanism for removably securing the first thermal element relative to the container, wherein the first thermal element comprises a housing that contains a phase-change material. An apparatus for containing one or more edible items includes a container having a base and a wall, a thermal element having a housing that contains a phase-change material, wherein the thermal element is selectively placeable at a first position and a second position, a first securing mechanism for removably securing the thermal element relative to the container when the thermal element is at the first position, and a second securing mechanism for removably securing the thermal element relative to the container when the thermal element is at the second position. | 10-27-2011 |
20110276824 | NETWORK SWITCH WITH BACKUP POWER SUPPLY - A network switch apparatus includes a housing, a first network port, a second network port, a first instrument port, an active component inside the housing, wherein the active component is configured to receive packets from the first network port, and pass at least some of the packets from the first network port to the first instrument port, a connector for supplying power from a power supply to the active component, and a backup power supply for supplying power to the active component when the active component does not receive power from the power supply. | 11-10-2011 |
20120023340 | NETWORK SWITCH WITH POWER OVER ETHERNET - A network switch apparatus includes a network switch housing, a first network port, a second network port, a first instrument port configured to communicate with a monitoring tool, wherein the first instrument port comprises a first power over Ethernet port configured to receive power, a transformer coupled to the first instrument port, and an active component inside the network switch housing, wherein the active component is configured to receive packets from the first network port, and pass at least some of the packets from the first network port to the first instrument port. | 01-26-2012 |
Patent application number | Description | Published |
20090121910 | Method and System for a Control Scheme on Power and Common-Mode Voltage Reduction for a Transmitter - Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell. | 05-14-2009 |
20100080271 | METHOD AND SYSTEM FOR A CONTROL SCHEME ON POWER AND COMMON-MODE VOLTAGE REDUCTION FOR A TRANSMITTER - Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The transmitter includes a plurality of current cells. Each cell is configurable for operating in different modes. The method includes determining a first probability associated with transmitting data at a particular symbolic level and determining a second probability associated with each cell being used during a transmission at the particular symbolic level. Next, one of the modes for each cell is selected in accordance with anticipated performance requirements. An average current of the transmitter is then calculated based upon the determined first and second probabilities and the selected modes. | 04-01-2010 |
20100117685 | Method and System for Detecting and Identifying Electronic Accessories or Peripherals - Aspects of a method and system for detecting and identifying electronic accessories or peripherals utilizing a hardware audio CODEC are provided. In this regard, a hardware audio CODEC may be operable to compare one or more voltages on one or more biased pins of an accessory or peripheral port to one or more reference voltages and generate one or more digital representations of the one or more voltages on the biased one or more pins. An accessory or peripheral attached to the accessory or peripheral port may be identified based on the comparison and/or the generated one or more digital representations. The one or more bias voltages may be controlled based on a result of the comparison and/or the generated digital representations. The one or more bias voltages may be reduced after an attached accessory or peripheral has been identified. | 05-13-2010 |
20150066438 | Low-power data acquisition system and sensor interface - A sensor interface includes on-chip relaxation oscillator circuit and a PLL that operate cooperatively to generate a highly accurate clock signal on-chip using low-power components. A photodiode generates a current signal based on an optical signal that is representative of a sensor signal. An ADC that operates based on the highly accurate clock signal generates a digital signal based on the current signal generated by the photodiode, and a processor processed the digital signal to estimate sensor data within the sensor signal. Examples of characteristics that may be sensed can include environmental characteristics (e.g., temperature, humidity, barometric pressure, etc.) and/or biomedical characteristics (e.g., body temperature, heart rate, respiratory rate, blood pressure, etc.). In desired, an amplifier processes the photodiode-provided current signal before it is provided to the ADC. Also, one or more CDACs that generate feedback currents may be used to reduce noise sensitivity of the sensor interface. | 03-05-2015 |