Patent application number | Description | Published |
20100321660 | METHOD AND APPARATUS FOR REDUCING DOWN TIME OF A LITHOGRAPHY SYSTEM - An apparatus includes a radiation source that emits a radiation beam that causes substantially all of a quantity of material to evaporate; and structure having first and second surface portions, a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion, and a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion. A different aspect involves emitting a radiation beam toward a quantity of material, the radiation beam causing substantially all of the quantity of material to evaporate; operating a structure having first and second surface portions in a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion; and thereafter operating the structure in a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion. | 12-23-2010 |
20110024924 | METHOD AND STRUCTURE OF STACKING SCATTEROMETRY-BASED OVERLAY OR CD MARKS FOR MARK FOOTPRINT REDUCTION - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch. | 02-03-2011 |
20110076843 | LITHOGRAPHY PATTERNING METHOD - A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer. | 03-31-2011 |
20110083496 | SEMICONDUCTOR PROCESSING APPARATUS WITH SIMULTANEOUSLY MOVABLE STAGES - A method and apparatus provide for simultaneously moving multiple semiconductor wafers in opposite directions while simultaneously performing processing operations on each of the wafers. The semiconductor wafers are orientated in coplanar fashion and are disposed on stages that simultaneously translate in opposite directions to produce a net system momentum of zero. The die of the respective semiconductor wafers are processed in the same spatial sequence with respect to a global alignment feature of the semiconductor wafer. A balance mass is not needed to counteract the motion of a stage because the opposite motions of the respective stages cancel each other. | 04-14-2011 |
20110161893 | LITHOGRAPHIC PLANE CHECK FOR MASK PROCESSING - The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired. | 06-30-2011 |
20110194086 | WAFER EDGE EXPOSURE MODULE - A wafer edge exposure module connected to a semiconductor wafer track system. The wafer edge exposure module includes a wafer spin device, an optical system, a scanner interface module, and a controller. The wafer spin device supports a wafer for processing. The optical system directs exposure light on a respective edge portion of the wafer simultaneously to create a dummy track on the edge of the wafer. The scanner interface module sends and/or receives dummy edge exposure information from a scanner via a computer network. The controller receives the dummy edge exposure information from the scanner interface module and uses the exposure information to control the optical system. | 08-11-2011 |
20120180813 | System and Method for Cleaning a Wafer Chuck - A wafer chuck is cleaned using a cleaning cap to remove processing residue and particulate matter. The cleaning cap is configured to overlie and align with the wafer chuck and includes a base and a first roller connected to the base and having wound therearound a cleaning cloth. The cleaning cap further includes a second roller connected to the base and having attached thereto a free end of the cleaning cloth. During use, the cleaning cloth winds upon the second roller from the first roller when the second roller rotates about its axis. The cleaning cap can be positioned relative the wafer chuck by way of a manipulator to ensure the cleaning cloth contacts the wafer chuck with sufficient force. The cleaning cloth rubs the wafer chuck with both translational motion and rotational motion. | 07-19-2012 |
20120180823 | In-Situ Immersion Hood Cleaning - An apparatus includes a wafer stage configured to secure a wafer; and a cleaning module including a tank adjacent to the wafer stage, and is positioned outside the region occupied by the wafer. The cleaning module is configured to receive de-ionized (DI) water into the tank and extract the DI water out of the tank. The tank is configured to hold DI water with a top surface of the DI water substantially level with a top surface of the wafer. | 07-19-2012 |
20130285264 | WAFER ASSEMBLY WITH CARRIER WAFER - A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark. | 10-31-2013 |
20130286395 | Tool Induced Shift Reduction Determination for Overlay Metrology - One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements. | 10-31-2013 |
20130309612 | ENHANCED SCANNER THROUGHPUT SYSTEM AND METHOD - A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned. | 11-21-2013 |
20140253901 | Two-Dimensional Marks - A method for controlling semiconductor production through use of a Focus Exposure Matrix (FEM) model includes taking measurements of characteristics of a two-dimensional mark formed onto a substrate, the two-dimensional mark including two different patterns along two different cut-lines, and comparing the measurements with a FEM model to determine focus and exposure conditions used to form the two-dimensional mark. The FEM model was created using measurements taken of corresponding two-dimensional marks formed onto a substrate under varying focus and exposure conditions. | 09-11-2014 |
20140257761 | Hybrid Focus-Exposure Matrix - A method for controlling semiconductor production through use of a hybrid Focus Exposure Matrix (FEM) model includes taking measurements of a set of structures formed onto a substrate. The method further includes using a FEM model to determine focus and exposure conditions used to form the structure The model was created through use of measurements of structures formed on a substrate under varying focus and exposure conditions, the measurements being taken using both an optical measurement tool and a scanning electron microscope. | 09-11-2014 |
20150076371 | LITHO CLUSTER AND MODULIZATION TO ENHANCE PRODUCTIVITY - The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process. | 03-19-2015 |
Patent application number | Description | Published |
20090206057 | Method To Improve Mask Critical Dimension Uniformity (CDU) - A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate. | 08-20-2009 |
20090258159 | NOVEL TREATMENT FOR MASK SURFACE CHEMICAL REDUCTION - A method includes forming an absorption material layer on a mask; applying a plasma treatment to the mask to reduce chemical contaminants after the forming of the absorption material layer; performing a chemical cleaning process of the mask; and performing a gas injection to the mask. | 10-15-2009 |
20100285399 | WAFER EDGE EXPOSURE UNIT - A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously. | 11-11-2010 |
20100308439 | DUAL WAVELENGTH EXPOSURE METHOD AND SYSTEM FOR SEMICONDUCTOR DEVICE MANUFACTURING - A dual wavelength exposure system provides for patterning a resist layer formed on a wafer for forming semiconductor devices, using two exposure operations, one including a first radiation having a first wavelength and the other including a second radiation including a second wavelength. Different or the same lithography tool may be used to generate the first and second radiation. For each die formed on the semiconductor device, a critical portion of the pattern is exposed using a first exposure operation that uses a first radiation with a first wavelength and a non-critical portion of the pattern is exposed using a second exposure operation utilizing the second radiation at a second wavelength. The resist material is chosen to be sensitive to both the first radiation having a first wavelength and the second radiation having the second wavelength. | 12-09-2010 |
20110159410 | COST-EFFECTIVE METHOD FOR EXTREME ULTRAVIOLET (EUV) MASK PRODUCTION - The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping. | 06-30-2011 |