Chang, Shanghai
Annie Chang, Shanghai CN
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20120173222 | METHOD AND SYSTEM FOR FACILITATING TEXT INPUT - A method and system for facilitating text input is disclosed. The method comprises: invoking an input assistant from within an application in an operating environment at a client, the input assistant being a standalone input service within the same operating environment as the application, receiving a text string from a user in an input field of the application, providing, by the input assistant, input prediction for completing the text string, selecting an input text of at least one word in the input field of the application, retrieving, by the input assistant, text content related to the input text from one or more text assistance services in communication with the input assistant, presenting the received text content to the user for assistance in the user's text input. | 07-05-2012 |
Clifford C. Chang, Shanghai JP
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20110174410 | FIBER-REINFORCED THERMOPLASTIC PIPE - Disclosed is a reinforced thermoplastic pipe, comprising a thermoplastic polymer inner tube, a thermoplastic polymer outer tube and a reinforcing fabric between the thermoplastic polymer inner tube and the thermoplastic polymer outer tube. The reinforcing fabric comprises thermosettable thermoplastic polymer weft yarns and unidirectionally woven warp yarns. The warp yarns are twisted into twisted cords. Disclosed is also a process of making the reinforced thermoplastic pipe. | 07-21-2011 |
Hsiang-Li Chang, Shanghai CN
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20100037071 | Using Internet to control delivery of power to a set of remote loads(devices) - This application describes an original concept, model, design, method and components of controlling delivery of power to one or many loads through the internet. It supports global power management as a service model. This service can be optimized with different criteria including but not limited to priority, efficiency, savings, costs, performance, season and time of the day . . . and this service can be implemented by computer software. The design consists of (i) Internet and its distributed data centers/computer clusters/databases/application software/Internet service provider (ii) a new type of web-enabled power cycler (iii) one or more gateway and another new type of wireless PAN/LAN/WAN-enabled power cyclers (iv) devices capable of accessing Internet for remote control. | 02-11-2010 |
Hsien Hao Chang, Shanghai CN
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20160063911 | Oled Display Device - The present application discloses an OLED display device. The OLED display device includes: a plurality of first Sub-pixels displaying a first color; a plurality of second sub-pixels displaying a second color; and a plurality of third sub-pixels displaying a third color. Areas of the third sub-pixels are greater than areas of the first sub-pixels, and are greater than areas of the second sub-pixels. The first sub-pixels and the second sub-pixels are alternately arranged in first columns; the third sub-pixels are arranged in second columns which are adjacent to the first columns; a distance between two third sub-pixels which are immediately adjacent to each other in a second column is a first distance, a distance between a first sub-pixel and a second stab-pixel which are alternately arranged in a first column is a second distance, and the first distance is smaller than the second distance. | 03-03-2016 |
Hsusheng Chang, Shanghai TW
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20140099783 | METHOD OF ADDING AN ADDITIONAL MASK IN THE ION-IMPLANTATION PROCESS - The present invention discloses a method of adding an additional mask in the ion-implantation process. It relates to technical field of ion implantation. This invention comprises: a mask plate is added upon the said MPW and the nitrogen element is implanted in the said MPW; the implanted nitrogen element is used for amorphizing the upper surface of the MPW. The advantageous effects of the above technical solution are as follows: the steps of the production process are simplified; the ion implantation mask will achieve 4 different doping concentrations of the ion implantation when the wafer is implanted. It means that it is possible to form 4 different gate oxide layers of different in thickness. However, it is essential to apply the photomask three times to achieve the same effect in the process of prior art. Consequently, the method of the present invention can reduce both the cost and the term of production process. | 04-10-2014 |
Hsusheng Chang, Shanghai CN
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20130064992 | Process for Eliminating Fog Particles on a Surface of High P Concentration PSG Film - A process for eliminating fog particles on a surface of a high P concentration PSG film is provided. The process mainly comprises steps of: feeding oxygen to a plasma environment in a reaction chamber; mixing plasma with oxygen; causing oxygen to react with unstable phosphorus atoms in the PSG film by using energy of plasma; and forming a passive film on the surface of the PSG film to prevent phosphorus in the PSG film from reacting with hydrogen and oxygen in the air. With the process for eliminating fog particles on a surface of a high P concentration PSG film, by feeding oxygen into the reaction chamber, the high-density plasma can be mixed with oxygen effectively, so as to achieve formation of the passive film on the surface of the phosphosilicate glass and thereby block water vapour from contacting boron and phosphorus to cause crystallization. | 03-14-2013 |
20130224399 | METHOD OF FORMING NITROGEN-FREE DIELECTRIC ANTI-REFLECTION LAYER - The present invention provides a method of forming a nitrogen-free dielectric anti-reflection layer comprising: introducing a reaction gas into the discharge tube until the reaction gas reaching a stable state; introducing the reaction gas into the reaction chamber and then generating a plasma, or generating a plasma and then introducing the reaction gas into the reaction chamber, wherein the time delay occurs between the two processes is utilized to perform the deposition of the nitrogen-free dielectric anti-reflection layer; finally stop introducing the reaction gas and then stop generating the plasma. The method can flexibly control the extinction coefficient and the refractive index of the nitrogen-free dielectric anti-reflection layer so as to obtain a straight photoresist pattern and greatly reduce the photoresist standing waves effect and photoresist poisoning effect. | 08-29-2013 |
20130227502 | ALGORITHM OF CU INTERCONNECT DUMMY INSERTING - The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect. | 08-29-2013 |
20130316539 | METHOD FOR REDUCING MORPHOLOGICAL DIFFERENCE BETWEEN N-DOPED AND UNDOPED POLYSILICON GATES AFTER ETCHING - The present invention discloses a method for reducing the morphological difference between N-doped and undoped poly-silicon gates after etching, comprising the following sequential steps: depositing a hard mask layer on a substrate template having N-doped poly-silicon and undoped poly-silicon to form an N-doped poly-silicon hard mask layer and an undoped poly-silicon hard mask layer respectively, and etching the undoped poly-silicon hard mask layer to make a thickness difference between the N-doped poly-silicon hard mask layer and the undoped poly-silicon hard mask layer; depositing an anti-reflection layer, and etching according to a predetermined pattern until exposing the N-doped poly-silicon, wherein when the N-doped poly-silicon is exposed, the undoped poly-silicon is etched to a certain degree; and removing residuals on the surface of the above formed structure, and etching to form an N-doped poly-silicon gate and an undoped poly-silicon gate, respectively. | 11-28-2013 |
20140077343 | DUMMY WAFER STRUCTURE AND METHOD OF FORMING THE SAME - A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity. | 03-20-2014 |
20140106475 | METHOD FOR ETCHING POLYSILICON GATE - A method for etching a polysilicon gate is disclosed, wherein the polysilicon gate includes an undoped polysilicon portion and a doped polysilicon portion that is situated on the undoped polysilicon portion. The method includes: obtaining a thickness of the undoped polysilicon portion and a thickness of the doped polysilicon portion by using an optical linewidth measurement device; and etching the undoped polysilicon portion and the doped polysilicon portion by using two respective steps with different parameters, respective etching time for the undoped polysilicon portion and the doped polysilicon portion of every wafer being adjusted in real time by using an advanced process control system. This method enables the doped and undoped polysilicon portions of each polysilicon gate on every wafer to have substantially consistent profiles between each other. | 04-17-2014 |
20140153000 | APPARATUS FOR DETECTING THE FLATNESS OF WAFER AND THE METHOD THEREOF - An apparatus for detecting the flatness of a top surface of a wafer includes a plurality of detector elements, a metal sink and a plurality of injection pipes. Each detector element comprises: a metal tube body, jet pipes, a light receiver and a light emitter. The method comprises: injecting ultra-pure water into the detector elements by injection pipes; emitting parallel beams along an upward-oblique direction, a preset Angle θ being formed between the beams and the vertical direction. The radiated beams above the water surface are incident on a receiver. The intensity of the beams received by the light receiver is used to calculate the height of the detecting point of the surface of the silicon wafer to determine the flatness condition of the wafer surface. The flatness of the photo-resist covered on the wafer surface can also be accurately measured by this method. | 06-05-2014 |
20150064930 | PROCESS OF MANUFACTURING THE GATE OXIDE LAYER - A process of manufacturing the gate oxide layer, which uses the wet oxidation by deuterium to form gate oxide layer, wherein the nitriding treatment is applied to formed gate oxide layer by high temperature annealing process, the stable Si-D bonds is formed on surface of the gate oxide layer to reduce silicon dangling bonds, which reduce the defect of the gate oxide interface and lower the interface defect density of the gate oxide layer and the charge density effectively to avoid NBTI, is provided. | 03-05-2015 |
Hsu Sheng Chang, Shanghai CN
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20150017785 | METHOD OF FORMING SALICIDE BLOCK WITH REDUCED DEFECTS - A method of forming a salicide block with reduced defects is disclosed, the method including performing an ultraviolet cure process on a silicon nitride layer deposited in a previous step. High-energy ultraviolet light used in the ultraviolet cure process breaks the hydrogen-containing chemical bonds such as silicon-hydrogen and nitrogen-hydrogen in the silicon nitride layer, and the dissociated hydrogen forms molecular hydrogen which is thereafter evacuated away by a vacuuming apparatus. In this way, the hydrogen content in the silicon nitride layer can be effectively decreased and the reaction between hydrogen in the silicon nitride layer and photoresist subsequently coated thereon can hence be reduced. As a result, a salicide block with reduced defects can be obtained, thus improving process reliability and product yield. | 01-15-2015 |
Jain Guang Chang, Shanghai CN
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20100190329 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 07-29-2010 |
Jason Chang, Shanghai CN
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20160141330 | METHOD FOR SEMICONDUCTOR SELECTIVE ETCHING AND BSI IMAGE SENSOR - A method of selectively etching a semiconductor device and manufacturing a BSI image sensor device includes etching a doped silicon substrate with an HNA solution for a predetermined time duration to obtain an etching solution having a concentration C | 05-19-2016 |
Jiang Guang Chang, Shanghai CN
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20100248468 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a photo resist material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 09-30-2010 |
Jianguang Chang, Shanghai CN
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20140054725 | TRANSISTOR DEVICE AND FABRICATION METHOD - Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption. | 02-27-2014 |
20150325671 | TRANSISTOR DEVICE - Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption. | 11-12-2015 |
Jian Guang Chang, Shanghai CN
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20100227464 | METHOD AND STRUCTURE FOIR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 09-09-2010 |
20100227465 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method forms at least one dielectric spacer within the first recessed region and at least one dielectric spacer within the second recessed region to form a resulting surface region, and subjects the resulting surface region to a chemical mechanical polishing process to cause formation of a substantially planarized second polysilicon layer free from the dielectric material. | 09-09-2010 |
Jicheng Chang, Shanghai CN
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20080242827 | Method for producing omni-meta aromatic polysulfonamide fiber - The invention relates to a method of preparing omni-meta aromatic polysulfonamide fiber which comprises three steps of preparing spinning dope, wet spinning and post treating. The said step of preparing spinning dope comprises the following steps: (1) dissolving 3,3′-diaminodiphenyl sulphone in a polar organic solvent and cooling it to −20˜20° C.; (2) adding m-phthaloyl chloride of the same mole of the 3,3′-diaminodiphenyl sulphone to carry out a polymerization reaction; (3) then adding an inorganic base of the same mole of 3,3′-diaminodiphenyl sulphone to neutralize the hydrogen chloride produced during the polymerization reaction. The spinning dope thus prepared has a polymer solid content of 10%-20%. The fiber prepared according to the method in the present invention has a greatly improved crimpability, and evidently increased elongation at break comparing with the conventional aromatic polysulfonamide fiber, so that the spinnability of resultant yarn is improved. | 10-02-2008 |
Jun Chang, Shanghai CN
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20150093929 | Connecting Terminal - A connecting terminal is disclosed having a wire connection portion with at least one pair of side arms, and an abutting portion attached at a second end to the wire connection portion. The Abutting portion includes at least one mating terminal receiving chamber and a locking structure. The locking structure includes a locking surface facing the wire connection portion and extending perpendicularly to an insertion direction of the connecting terminal, a first locking surface formed on an upper side of the abutting portion and a second locking surface formed on a lower side of the second end of the abutting portion. | 04-02-2015 |
Jung-Che Chang, Shanghai CN
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20100001738 | System and Method for Conducting Accelerated Soft Error Rate Testing - An apparatus for a user to conduct an accelerated soft error test (ASER) on a semiconductor sample is provided. The apparatus comprises a first component for holding the radiation source, where the radiation source may be either an alpha-particle or neutron-particle source. The apparatus comprises a second component for holding the semiconductor sample, where the semiconductor sample may be either a silicon wafer or semiconductor chip. The apparatus comprises a connecting assembly for placing the first component and the second component relative to each other at a plurality of positions that subject the semiconductor sample to a radiation stress from the radiation source at a plurality of stress efficiencies. Among the benefits provided are improved repeatability and credibility of ASER tests and reduced radiation exposures to operators of ASER tests. | 01-07-2010 |
Lee Chang, Shanghai CN
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20090200564 | Method and Structure for Fabricating Smooth Mirrors for Liquid Crystal on Silicon Devices - A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method includes forming an interlayer dielectric layer (e.g., BPSG, FSG) overlying the transistor layer. The method includes planarizing the interlayer dielectric layer and forming a sacrificial layer (e.g., bottom antireflective coating, polymide, photoresist, polysilicon) overlying the planarized interlayer dielectric layer. The method includes forming a plurality of recessed regions within a portion of the interlayer dielectric layer through the sacrificial layer while other portions of the interlayer dielectric layer remain intact. Preferably, lithographic techniques are used for forming the recessed regions. The method includes forming an aluminum layer (or other reflective layer or multilayers) to fill the recessed regions and overlying remaining portions of the sacrificial layer and selectively removing the aluminum layer overlying portions of the sacrificial layer to form a plurality of electrode regions corresponding to each of the recessed regions. | 08-13-2009 |
Nai-Shung Chang, Shanghai CN
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20150195906 | CIRCUIT BOARD AND ELECTRONIC ASSEMBLY - A circuit board including a first patterned conductive layer and a second patterned conductive layer isolated from the first patterned conductive layer is provided. The first patterned conductive layer has first signal traces and first ground traces. The second patterned conductive layer has second signal traces and second ground traces. An orthogonal projection of the second ground trace on the first patterned conductive layer partially overlaps at least one of the first signal traces. An orthogonal projection of the first ground trace on the second patterned conductive layer partially overlaps at least one of the second signal traces. An electronic assembly including the afore-described circuit board and a chip package connected thereto is also provided. | 07-09-2015 |
Ningjuan Chang, Shanghai CN
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20120092994 | TRAFFIC BEARER MAPPING METHOD AND COMMUNICATION DEVICE - Embodiments of the present invention provide a traffic bearer mapping method and a communication device. The traffic bearer mapping method includes: obtaining attribute information of a traffic data flow of a user; selecting a relay transmission tunnel according to the attribute information of the traffic data flow of the user; and mapping the received traffic data flow to the relay transmission tunnel for transmission, where the relay transmission tunnel includes a relay link radio bearer Un RB or a bearer including the Un RB. According to the embodiments of the present invention, transmission of a traffic data flow in an LTE-A network after a relay node is introduced into is implemented, thereby ensuring quality of service of multi-service. | 04-19-2012 |
Qing Chang, Shanghai CN
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20160133245 | Sound Processing Method And Terminal Device - A method comprising acquiring an analog first sound signal, performing analog-to-digital conversion on the first sound signal to generate a digital second sound signal, performing reverberation processing, at a system bottom layer, on the second sound signal to generate a digital third sound signal, performing digital sound mixing processing on the third sound signal and a background sound signal sent from an application layer to generate a digital fourth sound signal, performing digital-to-analog conversion on the fourth sound signal to generate an analog fifth sound signal, performing analog sound mixing processing on the first sound signal and the fifth sound signal to generate an analog sixth sound signal, and playing the sixth sound signal. | 05-12-2016 |
Qingjiang Chang, Shanghai CN
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20150030324 | OPTICAL TRANSMITTER - The optical transmitter includes a FP-LD, generating multiple-longitudinal mode light wave. The FP-LD is also driven by an electrical signal, modulates the electrical signal to the multiple-longitudinal mode light wave, and outputts the modulated multiple-longitudinal mode light wave. An optical coupler, coupled with the FP-LD, is used for feeding the modulated multiple-longitudinal mode light wave from the FP-LD to a fiber Bragg grating. The fiber Bragg grating is for filtering the received multiple-longitudinal mode light wave according to a parameter, and feeding back the optical signal generated after being filtered to the optical coupler. The optical coupler divides the optical signal, thus making the optical signal oscillate between the FP-LD and the fiber Bragg grating to form a oscillation cavity, and outputs a single mode optical wave with constant wavelength and power. | 01-29-2015 |
20150256285 | REMOTE NODE DEVICE, OPTICAL NETWORK UNIT AND SYSTEM AND COMMUNICATION METHOD THEREOF - A remote node device for mutual communication between optical network units in a passive optical network includes an N×N-arrayed waveguide grating configured to receive upstream optical signal of one of the optical network units and to output this signal as a first optical signal; a 1×2 wavelength division multiplexer configured to separate per band the first optical signal to obtain a second optical signal; and a 1×(N−1) power distributor configured to transmit the second optical signal to the corresponding optical network unit through the N×N-arrayed waveguide grating. | 09-10-2015 |
Richard Rugin Chang, Shanghai CN
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20120132941 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a light emitting device and a method for manufacturing a light emitting device. The light emitting device includes a base, an LED inversely mounted on the base. The LED includes an LED chip connected to the base and a buffer layer located on the LED. The buffer layer includes a plurality of depressions with complementary pyramid structure on a surface of the buffer layer not face the LED, the surface being a light-exiting surface of the LED. The buffer layer is made from silicon carbide. The light emitting device has a large area of the light-exiting surface and provides a reflecting film on a base, thus improving the luminous efficiency of the light emitting device. Inversely mounting mode is adopt, which is easy to implement. | 05-31-2012 |
20120261691 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a light emitting device, including a base, an LED inversely mounted on the base. The LED includes a buffer layer, an LED chip on the buffer layer. The buffer layer includes a plurality of protrusions with complementary pyramid structure on a light-exiting surface of the LED. The present invention also provides a method for manufacturing a light emitting device, including: providing a substrate and forming a plurality of pyramid structures on the substrate; forming successively a buffer layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer and a contact layer on the substrate with the pyramid structures; forming an opening with a depth at least from the contact layer to a top of the n-type semiconductor layer, and forming a first electrode on the contact layer and a second electrode on a bottom of the opening; and removing the substrate. The light emitting device has a high luminous efficiency and the manufacturing method is easy to implement. | 10-18-2012 |
20120273751 | LIGHT EMITTING DEVICE AND A MANUFACTURING METHOD THEREOF - The present invention provides a light emitting device and a method for manufacturing the light emitting device. The light emitting device includes a susceptor and a light emitting diode set on the susceptor. The light emitting diode includes an electrode layer connected to the susceptor and an LED die set on the electrode layer. The electrode layer is provided with a pyramid array structure surface and the pyramid array surface works as a reflective surface of the light emitting diode. The LED die is provided with an alveolate surface which works as the light exiting surface of the LED. According to the light emitting device provided in the present invention, the emanative light generated by the LED is emitted or reflected to a desired emitting direction. Further, the light emitting device has an alveolate light exiting surface and an LED having a pyramid array reflective surface, which increases the light emitting and reflective area of the LED, thereby improving the luminous efficiency. Besides, the light emitting device adopts a surface mount technology, which is easy to implement. | 11-01-2012 |
20130193406 | LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF - The present invention discloses an LED and its fabrication method. The LED comprises: a sapphire substrate; an epitaxial layer, an active layer and a capping layer arranged on the sapphire substrate in sequence; wherein a plurality of cone-shaped structures are formed on the surface of the sapphire substrate close to the epitaxial layer. The cone-shaped structures can increase the light reflected by the sapphire substrate, raising the external quantum efficiency of the LED, thus increasing the light utilization rate of the LED. Furthermore, the formation of a plurality of cone-shaped structures can improve the lattice matching between the sapphire substrate and other films, reducing the crystal defects in the film formed on the sapphire substrate, increasing the internal quantum efficiency of the LED. | 08-01-2013 |
20130214245 | LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF - The present invention discloses an LED and its fabrication method. The LED comprises: a substrate; an epitaxial layer, an active layer and a capping layer arranged on the substrate in sequence; wherein a plurality of microlens structures arc formed on the surface of the substrate away from the epitaxial layer, and a plurality of cams are formed on the surfaces of the microlens structures. When the light emitted from the active layer passes through the surfaces of the microlens structures or the surfaces of the cams, the incident angle is always smaller than the critical angle of total reflection, thus preventing total reflection and making sure that most of the light pass through the surfaces of the microlens structures and the cams, in this way improving external quantum efficiency of the LED, avoiding the rise of the internal temperature of the LED and improving the performance of the LED. | 08-22-2013 |
20130214309 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF, LIGHT EMITTING DEVICE - The present invention provides an LED and the manufacturing method thereof, and a light emitting device. The LED includes a first electrode, for connecting the LED to a negative terminal of a power supply; a substrate, located on the first electrode; and an LED chip, located on the substrate; in which a plurality of contact holes are formed through the substrate, the contact holes are evenly distributed and filled with electrode plugs connecting the first electrode to the LED chip. The light emitting device includes the LED, and further includes a base and an LED mounted on the base. The manufacturing method includes: providing a substrate; forming on the substrate an LED chip and a second electrode successively; forming a plurality of evenly distributed contact holes on a backface of the substrate, the contact holes extending through the substrate and to the LED chip; and filling the contact holes with conducting material till the backface of the substrate is covered by the conducting material. The LED has a high luminous efficiency and the manufacturing method is easy to implement. | 08-22-2013 |
20130216425 | ALUMINUM ALLOY MATERIAL AND METHOD OF MANUFACTURING ALUMINUM ALLOY BACKBOARD - The present invention discloses an aluminum alloy material, which is made of raw material of aluminum alloy. The raw material of aluminum alloy consists of the following constituents by percentage of weight: graphene: 0.1%˜1%, carbon nano tube: 1%˜5%, the rest being Al. The aluminum alloy material of the present invention has a good performance of heat dissipation, the thermal conductivity is higher than 200 W/m. Meanwhile, the present invention further provides a method of manufacturing aluminum alloy backboard, in which method, the raw material of aluminum alloy is heated and melted in a heating furnace, afterwards, the raw material of aluminum alloy after melting is formed into an aluminum alloy backboard by die-casting, in this way, the utilization rate of material is increased and the manufacturing cost of the backboard is reduced. | 08-22-2013 |
20130221387 | LIGHT EMITTING DIODE AND A MANUFACTURING METHOD THEREOF, A LIGHT EMITTING DEVICE - The present invention provides an LED and the manufacturing method thereof, and a light emitting device. The LED includes a first electrode, for connecting the LED to a negative electrode of a power supply; a substrate, located on the first electrode; and an LED die, located on the substrate; in which a plurality of contact holes are formed extending through the substrate, the diameter of upper parts of the contact holes is less than the diameter of lower parts of the contact holes, and the contact holes are filled with electrode plugs connecting the first electrode to the LED die. The light emitting device includes the LED, and further includes a susceptor and an LED mounted on the susceptor. The manufacturing method includes: forming successively an LED die and a second electrode on a substrate; patterning a backsurface of the substrate to form inverted trapezoidal contact holes which expose the LED die; and filling the contact holes with conductive material till the backface of the substrate is covered by the conductive material. The LED has a high luminous efficiency and the manufacturing method is easy to implement. | 08-29-2013 |
20130285550 | LIGHTING CIRCUIT - A lighting circuit comprises a first rectifying diode (D1), a second rectifying diode (D2), a third rectifying diode (D3), a fourth rectifying diode (D4), a first group of LEDs (LED11, . . . , LED1n), a second group of LEDs (LED21, . . . , LED2n), a third group of LEDs (LED31, . . . , LED3n), and a fourth group of LEDs (LED41, . . . , LED4n). The first group of LEDs (LED11, . . . , LED1n) is connected between the anode and the cathode of the first rectifying diode (D1); the second group of LEDs (LED21, . . . , LED2n) is connected between the anode and the cathode of the second rectifying diode (D2); the third group of LEDs (LED31, . . . , LED3n) is connected between the anode and the cathode of the third rectifying diode (D3); the fourth group of LEDs (LED41, . . . , LED4n) is connected between the anode and the cathode of the fourth rectifying diode (D4). | 10-31-2013 |
20130292640 | LIGHT EMITTING DIODE AND FORMING METHOD THEREOF - A light emitting diode (LED) and a forming method thereof are provided. The method for forming the LED includes: providing a semiconductor substrate ( | 11-07-2013 |
20150079713 | LIGHT EMITTING DIODE AND A MANUFACTURING METHOD THEREOF, A LIGHT EMITTING DEVICE - An LED includes a first electrode, for connecting the LED to a negative electrode of a power supply and a substrate located on the first electrode in which a plurality of contact holes are formed extending through the substrate. The diameter of upper parts of the contact holes is less than the diameter of lower parts of the contact holes, and the contact holes are filled with electrode plugs connecting the first electrode to the LED die. The light emitting device includes the LED, and further includes a susceptor and an LED mounted on the susceptor. The manufacturing method includes forming successively an LED die and a second electrode on a substrate, patterning a back surface of the substrate to form inverted trapezoidal contact holes which expose the LED die, and filling the contact holes with conductive material until the back face of the substrate is covered by the conductive material. | 03-19-2015 |
20150123162 | LIGHT EMITTING DIODE AND FORMING METHOD THEREOF - A light emitting diode (LED) and a forming method thereof are provided. The LED includes a semiconductor substrate, a bonding layer formed on a surface of the semiconductor substrate, and a LED die formed on a surface of the bonding layer. The effective lighting area of the LED may be increased, heat radiation may be improved, and lighting efficiency may be enhanced. | 05-07-2015 |
Richard Ru-Gin Chang, Shanghai CN
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20150024524 | Methods for Manufacturing Isolated Deep Trench and High-Voltage LED Chip - A method for manufacturing a deep isolation trench ( | 01-22-2015 |
Richard Rujin Chang, Shanghai CN
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20130207118 | LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF - The present invention discloses an LED and its fabrication method. The LED comprises: a substrate; an epitaxial layer, an active layer and a capping layer arranged on the substrate in sequence; wherein a plurality of bifocal microlens structures are formed on the surface of the substrate away from the epitaxial layer. When the light emitted from the active layer passes through the surfaces of the bifocal microlens structures, the incident angle is always smaller than the critical angle of total reflection, thus preventing total reflection and making sure that most of the light pass through the surfaces of the bifocal microlens structures, in this way improving external quantum efficiency of the LED, avoiding the rise of the internal temperature of the LED and improving the performance of the LED. | 08-15-2013 |
Ryan Chang, Shanghai CN
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20110053661 | MOBILE COMMUNICATION DEVICE WITH ERGONOMIC FEATURE - A mobile communication device with an ergonomic feature comprises a housing, a display unit, a first key module, and a second key module. The display unit is arranged on a lower part of one face of the housing, and the first key module is arranged on the housing on the same face as the display unit to locate closely above the display unit. The first key module comprises a plurality of upside keys which are arrayed into a laterally symmetric hexagonal configuration. The second key module comprises a plurality of lateral keys located on one of two opposite lateral surfaces of the housing. The keys of the two key modules are so arranged on the housing that either a right-handed or a left-handed user can conveniently operate the keys not only with a thumb but also the other four fingers while holding the device with one single hand. | 03-03-2011 |
Shouzhong Chang, Shanghai CN
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20150263508 | SYSTEM AND METHOD FOR DETECTING ISLANDING OF ELECTRICAL MACHINES AND PROTECTING SAME - In one aspect, a method for protecting one or more electrical machines during an islanding event is provided. The method includes connecting one or more electrical machines to an alternating current (AC) electric power system, wherein the AC electric power system is configured to transmit at least one phase of electrical power to the one or more electrical machines or to receive at least on phase of electrical power from the one or more electrical machines; electrically coupling at least a portion of a control system to at least a portion of the AC electric power system; coupling at least a portion of the control system in electronic data communication with at least a portion of the one or more electrical machines; and detecting an islanding of the one or more electrical machines based on one or more conditions monitored by the control system. | 09-17-2015 |
20160118786 | METHODS FOR OPERATING WIND TURBINE SYSTEM HAVING DYNAMIC BRAKE - Methods for operating a wind turbine system are provided. In one embodiment, a method includes adjusting a threshold direct current (DC) bus voltage for a dynamic brake in a wind turbine power converter above a reference DC bus voltage based on at least one system condition. The method further includes gating the dynamic brake on when an experienced DC bus voltage is equal to or greater than the threshold DC bus voltage, and inputting a dynamic brake condition into a controller when the dynamic brake is gated on. The method further includes determining if a grid fault has occurred, reducing power generation of the wind turbine if no grid fault has occurred, and blocking the power converter if a grid fault has occurred. The method further includes gating the dynamic brake off when the experienced DC bus voltage is less than the threshold DC bus voltage. | 04-28-2016 |
Suolin Chang, Shanghai CN
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20110305307 | NETWORK NODE, COMMUNICATION SYSTEM, AND METHOD FOR TRANSMITTING CLOCK PACKET THROUGH TUNNEL - A network node, a communication system, and a method for transmitting a clock packet through a tunnel are disclosed. The method includes: encapsulating a tunnel ingress clock packet received at an ingress of a tunnel in an encapsulation mode corresponding to the tunnel, and performing clock correction for the encapsulated clock packet; and sending the corrected clock packet to an egress of the tunnel. The network node for processing a clock packet includes an encapsulating module and a sending module. The communication system includes the network node for processing a clock packet, and further includes an intra-tunnel network node and a tunnel egress network node. According to the present invention, a clock packet is re-encapsulated and transmitted through a tunnel. In the subsequent process of transmitting the clock packet transparently, the node itself serves as a clock reference point, and all network nodes do not need to synchronize time absolutely. | 12-15-2011 |
Tsung Chih Chang, Shanghai CN
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20080290669 | Device For Controlling a Door - A device for controlling a door, the device having: a body; an electromagnet arranged to generate a magnetic field for retaining the door; a coupling that couples the electromagnet to the body, the coupling being arranged to allow a movement of the electromagnet relative to the body; and a current supply that is arranged to supply the electromagnet with a current. The current supply is arranged to detect the movement of the electromagnetic and to cease supplying the current at a predetermined instant after detecting the movement of the electromagnet. | 11-27-2008 |
20090174553 | ELECTROMAGNETIC DOOR LOCK - An electromagnetic door lock is described which includes at least two external generally planar surfaces and light emitting means; the light emitting means indicates the status of the lock and is arranged to emit light from the at least two external surfaces. | 07-09-2009 |
Tsung-Chin Chang, Shanghai CN
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20150308170 | Energy-Saving Magnetic Lock - An energy-saving magnetic lock comprising: a first lock module mounted to a part of a door such as a doorframe; and a second lock module, mounted to the other part of the door such as a door panel which can pivot about the doorframe, for interacting with the first lock module, wherein the first lock module comprises: an electromagnet ( | 10-29-2015 |
Venson Chang, Shanghai CN
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20110084718 | Burn-In Testing System - The present invention discloses a burn-in testing system including a burn-in board and a burn-in testing apparatus, the burn-in board including: a first interface component, adapted to connect with the burn-in testing apparatus for signal input and/or output between the burn-in board and the burn-in testing apparatus; and a second interface component, adapted to connect with a device under test for signal input and/or output between the burn-in board and the device, wherein the burn-in testing system further includes a pin matching unit flexibly connected with the burn-in board and adapted to adjust signal connection relationship between the first interface component and the second interface component according to a pin description of the device. By using the invention, burn-in tests of various devices having the same number of pins and different pin descriptions can be performed using the same burn-in board, which is compatible with existing burn-in boards, thereby improving production efficiency and reducing production costs. | 04-14-2011 |
Weiteng Chang, Shanghai CN
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20150096982 | PHOTORESIST CANISTER LINER - The disclosure discloses a photoresist canister liner comprises a liner body for containing photoresist comprising an upper portion and a tapered lower portion; an opening portion disposed at a top of the upper portion and comprising a photoresist outlet; and a diptube communicating with the photoresist outlet and inserted in the liner body and extending to a bottom of the lower portion. The lower portion of the liner body of the photoresist canister liner in the disclosure has diminishing section area, the photoresist can flow to the bottom of the liner body along the tapered lower portion and is collected in the bottom of the liner body, which prevents photoresist being wasted. | 04-09-2015 |
Wenfen Chang, Shanghai CN
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20150311188 | Methods of Fabrication and Testing of Three-Dimensional Stacked Integrated Circuit System-In-Package - The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies. | 10-29-2015 |
Wenjun Chang, Shanghai CN
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20150135342 | CELL LINE OF RENAL SARCOMATOID CARCINOMA IN PERSONS OF HAN NATIONALITY AND PREPARATION METHOD THEREOF - Provided is a renal sarcomatoid cell line RCC09HYF, of which the deposit No. is CCTCC C201130, and the preparation method of the renal sarcomatoid cell line. The renal sarcomatoid cell line RCC09HYF can grow for a long period and be steadily passaged in vitro. By tumorigenic experiments using in-situ animal models in vitro it has been found that: the tumorigenesis is relatively fast inside animals and 3-4 weeks after tumor inoculation, the transplanted tumors fill the whole abdominal cavity, and dyscrasia appears in above 50% of nude mice; moreover, lung metastasis is present in a few individuals. The renal sarcomatoid cell line RCC09HYF can provide an effective and steady cell model for further study of the genesis and metastasis mechanism of renal sarcomatoid carcinoma in persons of Han nationality and for clinical prediction, diagnosis and treatment. | 05-14-2015 |
Yande Chang, Shanghai CN
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20150242291 | STORAGE SYSTEM AND A METHOD USED BY THE STORAGE SYSTEM - Performing failover processing between a production host and a backup host, a storage system is connected to the production host and the backup host. In response to a failure of the production host, metadata is obtained of data blocks that have been cached from an elastic space located in a fast disk of the storage system. A storage capacity of the elastic space is expanded. Data blocks are obtained to which the metadata corresponds according to the metadata and the storage capacity of the expanded elastic space, and storing the same in the expanded elastic space. In response the backup host requesting the data blocks to which the metadata corresponds, and the data blocks to which the metadata corresponds have already been stored in the expanded elastic space, data blocks are obtained to which the metadata corresponds from the expanded elastic space and transmitting the same to the backup host. | 08-27-2015 |
Yoh Tz Chang, Shanghai CN
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20150103603 | METHODS FOR ERASING, READING AND PROGRAMMING FLASH MEMORIES - The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of −7V˜−10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC−6.5V˜VCC−4.5V, and its bit line is applied with a voltage of VCC+6V˜VCC+9V. In full consideration of factors including the chip manufacturing process, chip circuit design, chip quality and cost, optimal operating conditions fit for erasing, reading and programming, a NOR-type embedded 2T PMOS flash memory are determined. | 04-16-2015 |
Yu-Ming Chang, Shanghai CN
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20130100716 | HIGH-POWER MEDIUM-VOLTAGE DRIVE POWER CELL - The present invention provides a high-power medium-voltage drive power cell, which comprises: a rectifier module for rectifying the three-phase AC input voltage to get a DC voltage; an IGBT (Insulated Gate Bipolar Transistor) inverter bridge connected to capacitors for converting the DC voltage into an AC voltage of which the frequency, the amplitude and the phase are adjustable; a bypass module connected to the IGBT inverter bridge for providing the bypass function when the IGBT inverter bridge works in an abnormal state; and a heat pipe heat sink having a base plate on both sides of which power elements of the high-power medium-voltage drive power cell are disposed. | 04-25-2013 |
20130107458 | HEAT SINK DEVICE | 05-02-2013 |
Zhaohua Chang, Shanghai CN
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20130296806 | INTERVENTION MEDICAL DEVICE AND PREPARATION THEREOF - The present invention discloses an interventional medical device and methods of making the same. At least one coating layer is disposed on the outer surface of the interventional medical device and the material of the outmost layer of the coating layer is a sulfonate group-containing polymer. In the present invention, the material of the outmost layer of the interventional medical device is a sulfonate group-containing polymer. The polymer is endowed with a same surface property as that of heparin in addition to appropriate hydrophilicity due to the presence of the sulfonate group. After the interventional medical device is implanted into the human body, a hydrophilic surface is formed on the outer surface of the interventional medical device which is also negatively charged in the body fluid. Therefore, cells can easily adhere and grow on the outer surface thereof as a result of the enhanced cell compatibility. Furthermore, due to a surface property that is the same as that of heparin, the material is provided with excellent anticoagulant properties which inhibit the thrombosis and lower down the incidence rate of post-operational complications. | 11-07-2013 |
Zhigang Chang, Shanghai CN
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20120005242 | DIMENSION-BASED RELATION GRAPHING OF DOCUMENTS - Described herein is a technology for visualizing data. In accordance with some implementations, dimension metadata is automatically extracted from multiple documents. The extracted dimension metadata may be used to populate one or more relation dimensions. Based on the dimension metadata, one or more relations between the documents are determined along the one or more relation dimensions. A relation graph is presented to represent the documents interconnected by the one or more relations. | 01-05-2012 |
Zhongyuan Chang, Shanghai CN
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20090160487 | Phase and frequency detector with zero static phase error - A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced. | 06-25-2009 |
20100007641 | Voltage-mode line driving circuit having adaptive impedance matching - A voltage-mode line driving circuit is provided. The voltage-mode line driving circuit includes a driving circuit, the driving circuit receiving, as an input signal, a feedback signal, and outputting an output signal. The voltage-mode line driving signal also includes an adaptive tuning circuit coupled to the driving circuit, the adaptive tuning circuit receiving as input signals the feedback signal and the output signal and adaptively outputting a modifying signal to the driving circuit which modifies the feedback signal. | 01-14-2010 |
20100045389 | RING OSCILLATOR - A ring oscillator is disclosed for generating one or more clock signals. In some embodiments, the ring oscillator includes a first set of n series coupled inverters, a second set of n series coupled inverters, a first reset switch configured to couple a last inverter of the first set of inverters to a first inverter of the second set of inverters and to generate a first signal edge, a second reset switch configured to couple a last inverter of the second set of inverters to a first inverter of the first set of inverters, and a cross-coupling circuit coupled between an output of an inverter of the first set of inverters to a corresponding output of an inverter of the second set of inverters. In some embodiments, 2n clock signals separated in phase by 360°/2n may be generated. | 02-25-2010 |