Chang, Zhubei City
Chen-Chien Chang, Zhubei City TW
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20140159197 | SELF-ALIGNED DEEP TRENCH CAPACITOR, AND METHOD FOR MAKING THE SAME - A method for forming a trench capacitor includes providing a substrate of a semiconductor material having a hard mask layer; etching the hard mask layer and the substrate to form at least one trench extending into the substrate; and performing pull-back etching on the hard mask layer. In the pull-back etching, a portion of the hard mask layer defining and adjacent to side walls of an opening of the at least one trench is removed. A resulting opening on the hard mask layer has a width dimension larger than a width dimension of an opening of the at least one trench extending into the substrate. The method further comprises doping the semiconductor material defining upper surfaces and sidewalls of the at least one trench to form a doped well region. | 06-12-2014 |
20140327109 | DEEP TRENCH CAPACITOR MANUFACTURED BY STREAMLINED PROCESS - The present disclosure provides a deep trench capacitor device. A first capacitor electrode is made up of a doped region of semiconductor substrate in which two or more trenches are arranged. A second capacitor electrode is made up of a continuous body of conductive material. The continuous body of conductive material includes a lower body portion filling the two or more trenches and an upper body portion extending continuously over the lower body portion. The upper body portion extends upwardly out of the trenches by a non-zero distance. A capacitor dielectric liner is arranged in the two or more trenches to separate the first and second capacitor electrodes. The capacitor dielectric liner extends continuously out of the two or more trenches along outer sidewalls of the upper body portion. | 11-06-2014 |
Cheng-Ji Chang, Zhubei City TW
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20130271198 | CLOCK GENERATION METHOD AND SYSTEM - The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock. | 10-17-2013 |
20140043082 | CLOCK GENERATION METHOD AND SYSTEM - The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock. | 02-13-2014 |
Cheng-Jyi Chang, Zhubei City TW
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20130009741 | INTEGRATED CIRCUIT TRANSFORMER - The invention provides an integrated circuit transformer disposed on a substrate. The integrated circuit transformer includes a first coiled metal pattern disposed on the substrate, comprising an inner loop segment and an outer loop segment. A second coiled metal pattern is disposed on the substrate, laterally between the inner loop segment and the outer loop segment. A dielectric layer is disposed on the first coiled metal pattern and the second coiled metal pattern. A first via is formed through the dielectric layer, electrically connecting to one of the first and second coiled metal patterns. A first redistribution pattern is disposed on the dielectric layer, electrically connecting to and extending along the first via, wherein the first redistribution pattern covers at least a portion of the first coiled metal pattern and at least a portion of the second coiled metal pattern. | 01-10-2013 |
Cheng-Wen Chang, Zhubei City TW
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20140240884 | OVER CURRENT PROTECTION CIRCUIT - The over current protection circuit is coupled to a current path between an output end of a switch and a load. The over current protection circuit includes a first over current detection unit, a second over current detection unit and a control unit. The first over current detection unit is disposed between the current path and a first voltage, and generates a first control signal according to a current in the current path. The second over current detection unit is disposed between the current path and a second voltage, and generates a second control signal according to a current in the current path. The control unit is coupled with the first over current detection unit and the second over current detection unit, and controls the switch according to the first control signal or the second control signal to reduce the current in the current path. | 08-28-2014 |
20140292393 | GATE VOLTAGE GENERATING CIRCUIT - A gate voltage generating circuit to provide a gate voltage to a transistor switch is disclosed. The gate voltage generating circuit includes a first voltage generating circuit and a second voltage generating circuit. The first voltage generating circuit supplies a first voltage to a gate electrode of the transistor switch. The second voltage generating circuit supplies a second voltage to the gate electrode of the transistor switch. The second voltage is larger than a voltage to turn on the transistor switch. The first voltage is larger than the second voltage. | 10-02-2014 |
Chia-Chi Chang, Zhubei City TW
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20160103156 | SYSTEM AND METHOD FOR MEASURING LOAD IMPEDANCE - According to one embodiment of a system for measuring a load impedance, comprising: a switch module, a first reference impedance, a second reference impedance, and a control module, wherein the switch module connects the first reference impedance, the second reference impedance, and the load impedance, respectively; the control module connects the switch module; the control module connects the first reference impedance via controlling the switch module to obtain a first voltage value; the control module connects the second reference impedance via controlling the switch module to obtain a second voltage value; the control module connects the load impedance via controlling the switch module to obtain a load voltage value; and the control module calculates the measured value of the load impedance according to the first voltage value, the second voltage value, and the load voltage value. | 04-14-2016 |
Chia-Jung Chang, Zhubei City TW
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20140140107 | ISOLATED POWER CONVERTER, INVERTING TYPE SHUNT REGULATOR, AND OPERATING METHOD THEREOF - An isolated power converter, an inverting type shunt regulator, and an operating method thereof are disclosed. The isolated power converter includes a transformer, an inverting type shunt regulator, a controller, and an optocoupler. The inverting type shunt regulator is located on the secondary side of the transformer. The inverting type shunt regulator includes an error amplifier and a MOSFET. The controller is located on the primary side of the transformer. The controller includes an inverting unit cooperated with the MOSFET. The controller receives a feedback voltage. The optocoupler is coupled to the inverting type shunt regulator and the controller to provide an opto-coupling current to the controller. | 05-22-2014 |
Chien-Kuo Chang, Zhubei City TW
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20130119565 | Rotating Curing - A system for and a method of curing a material is provided. A material, such as an underfill material, is rotated during a curing process. The curing system may include a chamber, a holder to support one or more workpieces, and a rotating mechanism. The rotating mechanism rotates the workpieces during the curing process. The chamber may include one or more heat sources and fans, and may further include a controller. The curing process may include varying the rotation speed, continuously rotating, periodically rotating, or the like. | 05-16-2013 |
20150214074 | Packaging Methods for Semiconductor Devices, and Packaged Semiconductor Devices - Packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling a ring to a substrate, and coupling an integrated circuit die to the substrate within the ring. A molding material is disposed around the integrated circuit die within the ring. | 07-30-2015 |
Chih-Chia Chang, Zhubei City TW
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20140204034 | Touch Sensing And Feedback Apparatuses And Methods - A touch sensing and feedback apparatus comprises a feedback electrode, a reference electrode electrically insulated from the feedback electrode, a signal generator to generate a sensing driving signal and transmit the sensing driving signal to a sensing electrode, and a signal detector coupled to a detecting electrode to detect the sensing driving signal and generate a touch action signal based on the detected sensing driving signal. The signal generator generates a feedback driving signal and transmits the feedback driving signal to the feedback electrode based on the touch action signal, and generates a reference driving signal and transmits the reference driving signal to the reference electrode based on the touch action signal. The reference driving signal maintains the reference electrode electrically-grounded. | 07-24-2014 |
20150189736 | FLEXIBLE ELECTRONIC MODULE - A flexible electronic module is provided, including a flexible substrate having a supporting portion, a body portion, and a connection portion, wherein the supporting portion is connected with the body portion via the connection portion; a first trench formed between the supporting portion and the body portion; an electronic component disposed over a portion of the supporting portion; and a conductive line disposed over the supporting portion, the connection portion, and the body portion for connecting the electronic component. | 07-02-2015 |
20150293624 | TOUCH PANEL - A touch panel may include a substrate, a touch unit region and a covering layer. The touch unit region includes first electrode and a second electrode isolated from the first electrode. The covering layer covers at least one of the first electrode and the second electrode and has a touch surface. A distance between the touch surface and the first electrode or the second electrode ranges between 0.01 micrometers and 100 micrometers. A mutual capacitance value between the first electrode and the second electrode ranges between 0.1 pF and 10 pF when a touch has not occurred yet. | 10-15-2015 |
Chih-Kuang Chang, Zhubei City TW
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20120322247 | METHOD FOR FABRICATING HIGH VOLTAGE TRANSISTOR - A method for fabricating a high voltage transistor includes the following steps. Firstly, a substrate is provided. A first sacrificial oxide layer and a hard mask layer are sequentially formed over the substrate. The hard mask layer is removed, thereby exposing the first sacrificial oxide layer. Then, a second sacrificial oxide layer is formed on the first sacrificial oxide layer. Afterwards, an ion-implanting process is performed to introduce a dopant into the substrate through the second sacrificial oxide layer and the first sacrificial oxide layer, thereby producing a high voltage first-type field region of the high voltage transistor. | 12-20-2012 |
Chih-Lien Chang, Zhubei City TW
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20130335042 | Power Converter and Operating Method Thereof - A power converter including a multi-phase output stage, a comparator, and a time calculating unit is disclosed. The multi-phase output stage includes a plurality of channels. The comparator compares a first input signal with a second input signal to provide a setting signal. The time calculating unit adjusts on time duty cycles of the channels with the variation of the load according to the setting signal. When the load becomes larger, the frequency that the comparator provides the setting signal will be increased to cause that the on time duty cycles of the channels are overlapped. | 12-19-2013 |
20140340064 | POWER CONVERTER AND OPERATING METHOD THEREOF - A power converter is disclosed. The power converter includes a comparator and a timing generator. The comparator compares a first input signal with a second input signal to provide a control signal. The timing generator is coupled to the comparator. The timing generator includes a plurality of timing generating units, a logic unit, and a calculation unit. The timing generator generates a plurality of timing signals through the timing generating units and the logic unit according to the control signal, and the calculation unit forms a pulse width modulation (PWM) signal according to the timing signals. At least a part of the timing signals are overlapped. | 11-20-2014 |
Ching-Ting Chang, Zhubei City TW
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20140340836 | Modular USB Flash Drives with Replaceable Housings - A USB flash drive, comprising a housing comprising internal walls defining a receiving space, at least one of the internal walls having an engagement component, a memory main body disposed in the receiving space and comprising a hook slot component, and a fastener disposed in the receiving space comprising a protrusion component and a hook component, the hook component engaged with the hook slot component of the memory main body, and the protrusion component engaged with the engagement component of the housing, thereby fastening the memory main body to the housing. | 11-20-2014 |
20160081213 | Modular USB Flash Drives With Replaceable Housings - A USB flash drive, comprising a housing comprising internal walls defining a receiving space, at least one of the internal walls having an engagement component, a memory main body disposed in the receiving space and comprising a hook slot component, and a fastener disposed in the receiving space comprising a protrusion component and a hook component, the hook component engaged with the hook slot component of the memory main body, and the protrusion component engaged with the engagement component of the housing, thereby fastening the memory main body to the housing. | 03-17-2016 |
Chi-Shen Chang, Zhubei City TW
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20130169931 | AUTO-FOCUSING DIAGNOSTIC EQUIPMENT - A diagnostic equipment having an auto-focusing function comprising a image detection device, a first scanning device, a mobile optical lens assembly, a focusing detection device and a first splitter assembly is provided. The image detection device comprises a first light source and a first photo detector. The first light source provides a first incident light and the first incident light incident to an object and becomes a first signal light. The first photo detector is for receiving the first signal light. The first scanning device is for adjusting a path of the first incident light and to scan the object. The mobile optical lens assembly has a lens and a mobile platform. The first splitter assembly is for transmitting the first and the second signal light to the first and the second photo detector, respectively. | 07-04-2013 |
Chuan Chung Chang, Zhubei City TW
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20100215219 | METHOD AND APPARATUS FOR EXTRACTING SCENERY DEPTH INFORMATION - A method and optical apparatus are utilized not only to increase the degree of the similarity of the point spread functions of different fields of view, but also to maintain the degree of the difference of point spread functions which are along the optical axis of the optical apparatus. Using the degree of the difference of on-axis point spread functions, the depth information of scenery can be extracted. | 08-26-2010 |
20110249028 | PROJECTION SYSTEM WITH EXTENDING DEPTH OF FIELD AND IMAGE PROCESSING METHOD THEREOF - A projection system comprises an image input element and an optical imaging element. The image input element is configured to input an original image or a processed image. The optical imaging element, an optical system with axisymmetrical structure and specific spherical aberration, is configured to generate an image with extended depth of field on an image projection surface in accordance with the original image or the processed image. | 10-13-2011 |
20150117718 | METHOD AND SYSTEM FOR MEASURING DISTANCE - A method and a system for measuring a distance from a reference point to an object are provided. The method comprises the following steps. At least one image of an object is captured through a lens comprising a phase mask composed of a parallel plate and a wedge prism. At least two corresponding regions of interest (ROI) are obtained from the images. The regions of interest correspond to identical portions of the object. The relative coordinates between corresponding locations within the corresponding regions of interest is measured. The distance is calculated according to the relative coordinates. | 04-30-2015 |
Chu-Hsin Chang, Zhubei City TW
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20130253867 | Signal Processing Method and Associated Apparatus - A signal processing apparatus for receiving a spectral line of an original signal includes a starting point determining module, a searching module and a symbol rate determining module. The starting point determining module finds a maximum energy in the spectral line and determines at least one search starting point according to the maximum energy. From the at least one search starting point, the searching module searches along the spectral line towards a region with a lower energy for at least one minimum energy satisfying a predetermined condition. The symbol rate determining module determines a symbol rate of the original signal according to the at least one minimum energy. | 09-26-2013 |
20130258201 | SIGNAL PROCESSING APPARATUS AND ASSOCIATED METHOD - A signal processing apparatus includes an initial detecting module, a mixer, a symbol rate detecting module, a judging module and a correcting module. The initial detecting module determines an initial carrier frequency offset of an input signal according to a spectrum of the input signal. The mixer adjusts the input signal according to the initial carrier frequency offset to generate a frequency-compensated signal. The symbol rate detecting module determines a symbol rate of the input signal. The judging module judges whether the initial carrier frequency offset is correct according to the frequency-compensated signal. When a judgment result of the judging module is negative, the correcting module determines a corrected carrier frequency offset according to the symbol rate and the spectrum. | 10-03-2013 |
Chung-Yao Chang, Zhubei City TW
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20120076173 | Method and Device for Implementation of Adaptive Frequency Hopping by Power Spectral Density - A wireless communication device is disclosed. The wireless communication device includes a frequency hopping communication circuit, a power spectral density circuit and a control circuit. The frequency hopping communication circuit includes a channel map. The frequency hopping communication circuit selects one of channel in a channel map to connect to another frequency hopping communication circuit according to the channel map. The power spectral density circuit for generating a power spectral density signal by measuring spectrums on all channels connected to the frequency hopping communication circuit. The control circuit receives the power spectral density and output statistical distribution data to the frequency hopping communication circuit. The frequency hopping communication circuit updates the channel map according to the statistical distribution data. | 03-29-2012 |
20130051438 | WIRELESS COMMUNICATION CIRCUIT SUPPORTING ANTENNA DIVERSITY - A wireless communication circuit is disclosed including: a transceiver for transmitting and receiving signals; and a control circuit coupled with the transceiver for controlling a switching circuit to switch the transceiver to a first antenna set for a first time period and then to switch the transceiver to a second antenna set for a second time period in a test period. If a throughput statistic of the first antenna set with respect to the test period is greater than that of the second antenna set, the control circuit configures the switching circuit to switch the transceiver to the first antenna set after the test period. | 02-28-2013 |
20130176878 | WIRELESS COMMUNICATION CIRCUIT SUPPORTING ANTENNA DIVERSITY - A wireless communication circuit for a wireless communication device having a plurality of antennas is disclosed. The wireless communication circuit includes: a transceiver for receiving and transmitting network packets; a control circuit for controlling the switching circuit to switch the transceiver among the antennas so that the transceiver receives the preamble of a first network packet; and a receiving signal strength detector for detecting the receiving signal strength value of respective antennas in respective receiving periods during the reception of the preamble conducted by the transceiver. If the receiving signal strength value of each antenna is less than a predetermined threshold, the control circuit selects an antenna with the maximum receiving strength value as a target antenna and controls the switching circuit to couple the transceiver to the selected target antenna so that the transceiver receives the rest of the first network packet through the target antenna. | 07-11-2013 |
20130203370 | WIRELESS COMMUNICATION RECEIVER AND METHOD THEREOF - A wireless communication receiver includes a circuit, an analog-to-digital converter (ADC) and a processing circuit. The circuit receives a wireless signal and outputs an analog signal according to a gain index. The ADC converts the analog signal to a digital signal. The processing circuit adjusts the gain index according to a clipping number of the ADC. | 08-08-2013 |
20130316660 | WIRELESS APPARATUS AND INTERFERENCE DETERMINATION METHOD THEREOF - A wireless apparatus and an interference determination method thereof are provided. The wireless apparatus determines that the wireless apparatus operates in a first bandwidth mode, and counts a first clear channel assessment (CCA) number associated with a primary channel, a second CCA number associated with a secondary channel, an entire CCA number associated with either the primary channel or the secondary channel, and the false alarm number according to at least one received radio frequency (RF) signal. Afterwards, the wireless apparatus determines that the second CCA number exceeds the summation of the first CCA number and bias number to determine that it is in an interference state, and determines that the interference state belongs to either the first interference type or second interference type according to the radio of the entire CCA number to the FA number. | 11-28-2013 |
Chun Hua Chang, Zhubei City TW
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20120319239 | SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME - A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A first etch stop layer is disposed over the TSV structure. A first dielectric layer is disposed in contact with the first etch stop layer. A first conductive structure is disposed through the first etch stop layer and the first dielectric layer. The first conductive structure is electrically coupled with the TSV structure. The TSV structure is substantially wider than the first conductive structure. A second etch stop layer is disposed in contact with the first dielectric layer. A metal-insulator-metal (MIM) capacitor structure is disposed in contact with the second etch stop layer. | 12-20-2012 |
20130193578 | THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening. | 08-01-2013 |
20130285200 | Capacitor for Interposers and Methods of Manufacture Thereof - Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate. | 10-31-2013 |
20130320493 | CAPACITOR FOR INTERPOSERS AND METHODS OF MANUFACTURE THEREOF - Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers. | 12-05-2013 |
20140015101 | SEMICONDUCTOR STRUCTURES HAVING A METAL-INSULATOR-METAL CAPACITOR STRUCTURE - A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A metal-insulator-metal (MIM) capacitor structure is disposed over the substrate. A dual damascene structure disposed over and electrically coupled with the TSV structure, wherein the dual damascene structure includes a via portion and a trench portion A first dielectric layer is disposed around the via portion of the dual damascene structure. A second dielectric layer disposed around the trench portion of the dual damascene, wherein the second dielectric layer is disposed over the MIM capacitor structure. | 01-16-2014 |
20140017873 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - A method of forming a semiconductor structure includes forming a through-substrate-via (TSV) structure in a substrate. The method includes forming a first etch stop layer over the TSV structure. The method further includes forming a first dielectric layer in contact with the first etch stop layer. The method still further includes forming a second etch stop layer in contact with the first dielectric layer. The method also includes forming a metal-insulator-metal (MIM) capacitor structure in contact with the second etch stop layer. The method further includes forming a first conductive structure through the first etch stop layer and the first dielectric layer, wherein the first conductive structure is electrically coupled with the TSV structure and the TSV structure is substantially wider than the first conductive structure. | 01-16-2014 |
20150037960 | METHOD OF MANUFACTURING A CAPACITOR - A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor. | 02-05-2015 |
20150048483 | SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME - A metal insulator metal (MIM) capacitor includes a base layer and a copper bulk layer in the base layer. The MIM capacitor further includes an etch stop layer over the base layer and the copper bulk layer and an oxide-based dielectric layer over the etch stop layer. The MIM capacitor further includes a capacitor bottom layer over the oxide-based dielectric layer, an insulator layer over the capacitor bottom layer, and a capacitor top layer over the insulator layer. | 02-19-2015 |
20150130082 | Configurable Routing for Packaging Applications - Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof. | 05-14-2015 |
Chun-Jong Chang, Zhubei City TW
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20120168712 | HIGH BRIGHT LIGHT EMITTING DIODE - A high bright LED comprises a substrate, a conductive layer, a first semiconductor layer, a luminous layer, a second semiconductor layer, a first electrode, a second electrode and an insulation structure. The conductive layer, the first semiconductor layer, the luminous layer and the second semiconductor layer are disposed upwards from an upper solder layer of the substrate in order. The first electrode is electrically connected to the conductive layer The second electrode penetrates through the conductive layer, the first semiconductor layer and the luminous layer to make the upper solder and the second semiconductor layer electrically connected. The insulation structure comprises at least two passivation layers peripherally wrapping the second electrode. The thicknesses of the at least two passivation layers are conformed to the distributed Bragg reflection technique to make the passivation layers jointly used as a reflector with high reflectance. | 07-05-2012 |
20160119994 | Solid State Light Source Device and Dimming Circuit Thereof - A solid state light source device and a dimming circuit are provided. The dimming circuit includes a rectifier circuit, a switch unit, and a control unit. The rectifier circuit is configured to convert an AC voltage signal to a rectified voltage signal. The switch unit is electrically connected between the rectifier circuit and a lighting module and configured to undergo switching according to a pulse width modulation signal to connect or disconnect the rectifier circuit and the lighting module. The control unit is electrically connected to the switch unit and configured to generate the pulse width modulation signal to control the switch unit. | 04-28-2016 |
Horng-Der Chang, Zhubei City TW
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20160105107 | APPARATUS AND METHOD OF PULSE WIDTH MODULATION WITH FEEDBACK CONTROL - According to one embodiment an apparatus of pulse width modulation with feedback control, adapted to drive an external load, the apparatus comprising a pulse width modulator, an adjustment encoder, a power driver, and a controller, wherein the pulse width modulator transfers a pulse code modulation code into a pulse width modulation code, the adjustment encoder transfers the pulse width modulation code into an upper-driven signal and a lower-driven signal, the power driver receives the upper-driven signal and the lower-driven signal to drive the external load, the controller measures the voltage of the external load to generate a control signal according to the upper-driven signal and the lower-driven signal, and transmits the control signal to the adjustment encoder to adjust the upper-driven signal and the lower-driven signal. | 04-14-2016 |
Jui-Chuan Chang, Zhubei City TW
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20160129484 | SEMICONDUCTOR APPARATUS AND METHOD OF REMOVING PHOTORESIST LAYER ON SUBSTRATE - A semiconductor apparatus for removing a photoresist layer on a substrate includes a platform, a first ultraviolet lamp, and an ozone supplier. The platform is used to support the substrate. The first ultraviolet lamp is used to provide first ultraviolet light. The ozone supplier has at least one first nozzle for introducing ozone toward the substrate through the first ultraviolet light, such that at least a part of the ozone is decomposed by the first ultraviolet light, and at least a part of the decomposed ozone reaches the photoresist layer to react with the photoresist layer. Moreover, a method of removing a photoresist layer on a substrate is also provided. | 05-12-2016 |
Jui-Hsiang Chang, Zhubei City TW
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20130241760 | OBJECT DETECTION DEVICE AND METHOD THEREOF - An object detection device includes a RF emitter composed of a RF emitting module and an emitter antenna for emitting an EM wave, a RF receiver composed of a RF receiving module and a RF antenna for receiving a reflected EM wave by a predetermined object and a processor connected to the RF emitter and the RF receiver to process the received reflected EM wave so as to obtain a received signal strength indicator (RSSI) such that existence of the object is determined based on fluctuation of the RSSI when compared with a predetermined threshold value. | 09-19-2013 |
Kai-Fei Chang, Zhubei City TW
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20150195080 | DATA TRANSMISSION METHOD AND ASSOCIATED SIGNAL TRANSMITTER - A signal transmission method suitable for a signal transmitter includes: providing a plurality of clock signals with different phases, selecting some of the clock signals as a plurality of intermediate signals; transmitting the intermediate signals to a signal output circuit via a clock distribution network; selecting one of the intermediate signals as a reference clock of the signal output circuit to output data. | 07-09-2015 |
Keng-Hao Chang, Zhubei City TW
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20150063430 | TRANSCEIVER - The present invention provides a transceiver for a radio frequency identification (RFID) reader. The transceiver includes an RF front end, a transmitting component, a receiving component, a power divider and a micro control unit (MCU). The power divider has three terminals. The first terminal of the power divider is connected to the transmitting component. The second terminal of the power divider is connected to the receiving component. The third terminal is connected to the RF front end. Moreover, the MCU is connected to the transmitting component and the receiving component, and generates a transmitted signal and receives a retrieved data. According to the present invention, the transceiver further includes an RF switch, a matching circuit and a receiving circuit. | 03-05-2015 |
Liang-Wey Chang, Zhubei City TW
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20110270146 | Orthotic - An orthotic for correcting a movement of a hip joint of a user includes a support frame, a cam, a leg fixer, a following element and a restoring element. The support frame is attached to the user. The cam is disposed to the support frame. The leg fixer is pivotally connected to the support frame. The following element is moveably mounted on the leg fixer and connected to the cam. The restoring element connected to the leg fixer provides a force of restoring the leg fixer when the leg fixer is moved. When the leg fixer is being moved, a predetermined relative movement between the cam and the following element is produced to correct a movement range of the hip joint. | 11-03-2011 |
May Chang, Zhubei City TW
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20130069236 | EFFICIENT SEMICONDUCTOR DEVICE CELL LAYOUT UTILIZING UNDERLYING LOCAL CONNECTIVE FEATURES - Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules. | 03-21-2013 |
Ming-Yi Chang, Zhubei City TW
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20160042794 | LEVEL SHIFTER AND DECODER FOR MEMORY - A level shifter receiving an input with a relatively narrow voltage range and provides an output with a relatively wide voltage range. The level shifter including a transistor with a turn-on voltage. Control circuitry applies a bias to the level shifter such that the transistor does not receive the turn-on voltage. | 02-11-2016 |
Qi-Xin Chang, Zhubei City TW
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20150062138 | TIMING CONTROLLER FOR IMAGE DISPLAY AND ASSOCIATED CONTROL METHOD - A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase. | 03-05-2015 |
Shang-Wern Chang, Zhubei City TW
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20150296563 | BAKING APPARATUS FOR PRIMING SUBSTRATE - A baking apparatus for priming a substrate is provided, which includes a chamber, a hot plate and a barrier element. The hot plate is in the chamber and configured to bake the substrate on the hot plate. The barrier element is in contact with a periphery of the substrate and the hot plate to prevent contamination on a lower surface of the substrate. Another baking apparatus for priming a substrate is also provided, which includes a chamber and a hot plate. The hot plate is in the chamber and in full contact with a lower surface of the substrate to prevent contamination thereon. | 10-15-2015 |
20160025650 | OVERLAY METROLOGY METHOD AND OVERLAY CONTROL METHOD AND SYSTEM - The present disclosure provides an overlay metrology method, an overlay control method and an overlay control system. The overlay metrology method includes capturing a current layer image of a current overlay mark on a current layer with a current focal length and capturing a previous layer image of a previous overlay mark on a previous layer with a previous focal length. Then, the overlay metrology method further includes combining the current layer image with the previous layer image to form an overlay mark image and determining an overlay error between the current overlay mark and the previous overlay mark based on the overlay mark image. | 01-28-2016 |
Shao-Chang Chang, Zhubei City TW
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20150063430 | TRANSCEIVER - The present invention provides a transceiver for a radio frequency identification (RFID) reader. The transceiver includes an RF front end, a transmitting component, a receiving component, a power divider and a micro control unit (MCU). The power divider has three terminals. The first terminal of the power divider is connected to the transmitting component. The second terminal of the power divider is connected to the receiving component. The third terminal is connected to the RF front end. Moreover, the MCU is connected to the transmitting component and the receiving component, and generates a transmitted signal and receives a retrieved data. According to the present invention, the transceiver further includes an RF switch, a matching circuit and a receiving circuit. | 03-05-2015 |
Shih-Chien Chang, Zhubei City TW
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20150235294 | NETWORK SEARCHING SYSTEM AND SEARCHING METHOD THEREOF - A network searching system and a network searching method thereof are disclosed. The network searching system includes a plurality of servers and a searching host. Each of the servers includes a searching engine and stores at least one piece of merchandise information. The servers search the merchandise information therein via the respective searching engines. The searching host electrically connects to each of the servers. The searching host stores a retrieval program and a retrieval interface. The searching host imports the merchandise information respectively from the servers via the retrieval program and displays the merchandise information on the retrieval interface. Besides, the searching host receives a searching string and searches the merchandise information imported from the servers according to the searching string, generates the merchandise information matching the criterion of the searching string, and displays such merchandise information on the retrieval interface. | 08-20-2015 |
Shih-Ming Chang, Zhubei City TW
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20130270704 | Semiconductor Device with Self-Aligned Interconnects - A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface. | 10-17-2013 |
20130285246 | Semiconductor Device With Self-Aligned Interconnects and Blocking Portions - A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines. | 10-31-2013 |
20130292836 | VIA-FREE INTERCONNECT STRUCTURE WITH SELF-ALIGNED METAL LINE INTERCONNECTIONS - The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer. | 11-07-2013 |
20140157212 | Distinguishable IC Patterns with Encoded Information - A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used. | 06-05-2014 |
20140193981 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 07-10-2014 |
20140220493 | Self Aligned Patterning With Multiple Resist Layers - A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate. | 08-07-2014 |
20140264760 | Layout Optimization of a Main Pattern and a Cut Pattern - A method for feature pattern modification includes extracting both a main pattern and a cut pattern from a design pattern, the main pattern being laid out under a set of process guidelines that improve the process window during formation of the main pattern, and modifying at least one of: the main pattern and the cut pattern if either feature pattern is in violation of a layout rule. | 09-18-2014 |
20140264773 | SYSTEM AND METHOD FOR OPTIMIZATION OF AN IMAGED PATTERN OF A SEMICONDUCTOR DEVICE - In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter. | 09-18-2014 |
20140264899 | Pattern Modification with a Preferred Position Function - A method for pattern modification for making an integrated circuit layout is disclosed. The method includes determining a feature within a pattern of the integrated circuit layout that can be rearranged; determining a range in which the feature can be repositioned; for the feature, determining a preferred position function that exhibits extreme values at preferable positions; and rearranging the position of the feature within the range to match an extreme value of the function. | 09-18-2014 |
20140273442 | Spacer Etching Process For Integrated Circuit Design - A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. | 09-18-2014 |
20140273456 | Method for Integrated Circuit Patterning - A method of forming a target pattern includes forming a mandrel pattern on a substrate, the mandrel pattern having a line with a first dimension in a first direction and a second dimension in a second direction; forming a spacer around the mandrel pattern, the spacer having a first width; forming a cut pattern over the mandrel pattern and the spacer wherein the cut pattern partially overlaps the spacer on both sides of the line in the first direction; etching the mandrel pattern using the cut pattern as an etch mask, thereby defining a plurality of openings with sidewalls of the spacer, the cut pattern, and a portion of the mandrel pattern underneath the cut pattern; and reducing the first width of the spacer thereby to enlarge the plurality of openings. | 09-18-2014 |
20140377962 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 12-25-2014 |
20150070665 | Homogeneous Thermal Equalization with Active Device - A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece. | 03-12-2015 |
20150079774 | Self-Alignment for using Two or More Layers and Methods of Forming Same - Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material. | 03-19-2015 |
20150089458 | SYSTEMS AND METHODS FOR MITIGATING PRINT-OUT DEFECTS - The present disclosure provides methods and systems for mitigating print-out defects that result during semiconductor simulation and/or fabrication. One of the methods disclosed herein includes steps of receiving a first desired sub-layout and a second desired sub-layout and of optimizing the first desired sub-layout and the second desired sub-layout to generate a first optimized sub-layout and a second optimized sub-layout. The method further includes simulating the first optimized sub-layout and the second optimized sub-layout and of identifying one or more print-out defects in the simulated first optimized sub-layout and the simulated second optimized sub-layout. By comparing the simulated first optimized sub-layout and the simulated second optimized sub-layout it may be determined whether or not print-out defects in the simulated second optimized sub-layout are covered by the first desired sub-layout such that the first optimized sub-layout may be used to pattern material layers. | 03-26-2015 |
20150106771 | METHOD OF LITHOGRAPHIC PROCESS EVALUATION - Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model. | 04-16-2015 |
20150116678 | System and Method for Real-Time Overlay Error Reduction - Disclosed is a lithography system. The lithography system includes a radiation source to provide radiation energy for lithography exposure; a substrate stage configured to secure a substrate; an imaging lens module configured to direct the radiation energy onto the substrate; at least one sensor configured to detect a radiation signal directed from the substrate; and a pattern extraction module coupled with the at least one sensor and designed to extract a pattern of the substrate based on the radiation signal. | 04-30-2015 |
20150128098 | Method and System for Repairing Wafer Defects - A method of lithographic defect detection and repair is disclosed. In an exemplary embodiment, the method of patterning a workpiece comprises receiving a mask for patterning a workpiece. The mask is inspected for defects, and a mask defect is identified that is repairable in the workpiece. The workpiece is lithographically exposed using the mask, and a defect is repaired within the workpiece based on the identified mask defect. The method may further comprise comparing defects across the workpiece to determine repeating defects and determining a spacing between repeating defects. A distance between a first focal point and a second focal point of a lithographic system may be configured to correspond to the spacing between repeating defects. Thus, a first repeating defect and a second repeating defect may be repaired concurrently. | 05-07-2015 |
20150147887 | MECHANISMS FOR FORMING PATTERNS - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns. | 05-28-2015 |
20150248518 | MINIMIZING HARMFUL EFFECTS CAUSED BY RETICLE DEFECTS BY RE-ARRANGING IC LAYOUT LOCALLY - Provided is a method of fabricating a semiconductor device. An integrated circuit (IC) layout plan is obtained. The IC layout plan contains critical features and non-critical features. Locational information regarding a defect on a blank reticle is obtained. The blank reticle is a candidate reticle for being patterned with the IC layout plan. Based on the locational information regarding the defect and the IC layout plan, a determination is made that at some of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan, regardless of whether the IC layout plan is globally manipulated or not before being patterned onto the blank reticle. In response to the determination, selected local portions of the IC layout plan are re-arranged such that none of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan. | 09-03-2015 |
20150255283 | PHOTO RESIST TRIMMED LINE END SPACE - One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (HM) region is formed above a first HM region. Additionally, at least some of the first patterned second HM region is removed. In some embodiments, a first sacrificial HM region and a second sacrificial HM region are formed above at least one of the first patterned second HM region or the first HM region. Photo resist (PR) is patterned above the second sacrificial HM region, and a spacer region is deposited above the patterned PR and second sacrificial HM region. In some embodiments, at least some of at least one of the spacer region, the PR, or the respective sacrificial HMs is removed. In this way, a line end space structure associated with an end-to-end space is formed. | 09-10-2015 |
20150262830 | MECHANISMS FOR FORMING PATTERNS USING MULTIPLE LITHOGRAPHY PROCESSES - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern. | 09-17-2015 |
20150301447 | Self Aligned Patterning With Multiple Resist Layers - A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate. | 10-22-2015 |
20150303067 | MECHANISMS FOR FORMING PATTERNS - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns. | 10-22-2015 |
20150317424 | SYSTEM AND METHOD FOR OPTIMIZATION OF AN IMAGED PATTERN OF A SEMICONDUCTOR DEVICE - In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter. | 11-05-2015 |
We-Hsu Chang, Zhubei City TW
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20110084676 | CONTROL CIRCUIT AND METHOD FOR A POWER CONVERTER CONTROLLING ADAPTIVE VOLTAGE POSITION - A control circuit and method for a power converter controlling adaptive voltage position comprises an adder acquiring an output voltage difference between the output voltage and the reference output voltage, a digital compensator with an Z-domain transfer function to reference to the output voltage difference to generate a pulse width control signal, regulating the least significant bits of a denominator coefficient in the Z-domain transfer function such that a load line function of the power converter is performed via control of the pulse width control signal, and a pulse modulation circuit being controlled by the pulse width control signal to generate the pulse width modulation signal to control ON/OFF of power switch of the power converter. Thus, functions of controlling the negative or positive load lines and function of variable load line required by the operation of multiphase converter can be performed easily without complicated operations. | 04-14-2011 |
Wei-Chung Chang, Zhubei City TW
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20130150001 | Mobile device - The present invention discloses a mobile phone comprising a gravity sensor, a processor, and a memory. The gravity sensor senses inertia data along a specific direction, the processor couples with the gravity sensor and receives a output signal from the gravity sensor, and the memory stores at least one personal information and operates under the processor's control. When either the gravity sensor or the processor detects a vertical free-fall motion, the processor performs a information security process to lock the personal information to become inaccessible. | 06-13-2013 |
Wei Kei Chang, Zhubei City TW
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20150109049 | Electronic Device with PVT Delay Compensation and Related Method - An electronic device includes a first circuit, and a delay circuit electrically connected to the first circuit. The delay circuit includes a resistor, a capacitor, and a process, voltage or temperature (PVT) compensation circuit electrically connected to the capacitor. | 04-23-2015 |
Yao-Chung Chang, Zhubei City TW
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20160111501 | METHOD TO DEFINE THE ACTIVE REGION OF A TRANSISTOR EMPLOYING A GROUP III-V SEMICONDUCTOR MATERIAL - A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group III-V heterojunction. A gate has a ring shape and is arranged over the group III-V heterojunction around the inner drain electrode. An outer source electrode has a ring-shaped region arranged over the group III-V heterojunction around the gate. A method for manufacturing the group III-V transistor device is also provided. | 04-21-2016 |
Yao Wen Chang, Zhubei City TW
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20150194311 | Method For Manufacturing Semiconductor Device - A method for forming a semiconductor device includes forming a gate structure over a substrate, performing a lightly-doped drain (LDD) implantation of first dopant ions into the substrate using the gate structure as a mask to form LDD regions in the substrate, performing, after the LDD implantation, a pre-amorphization implantation (PAI) into the substrate using the gate structure as a mask to pre-amorphize at least a portion of the LDD regions, and performing, after the PAI, a high-doping implantation of second dopant ions into the substrate using the gate structure as a mask to form highly-doped regions at least partially overlapping the LDD regions. | 07-09-2015 |
20150194420 | Semiconductor Device - A semiconductor device includes a substrate, and first and second wells formed in the substrate. The first well has a first conductivity type. The second well has a second conductivity type different than the first conductivity type. The device includes a first heavily-doped region having the first conductivity type and a second heavily-doped region having the first conductivity type. A portion of the first heavily-doped region is formed in the first well. The second heavily-doped region is formed in the second well. The device also includes an insulating layer formed over a channel region of the substrate between the first and second heavily-doped regions, and a gate electrode formed over the insulating layer. The device further includes a terminal for coupling to a circuit being protected, and a switching circuit coupled between the terminal and the first heavily-doped region, and between the terminal and the gate electrode. | 07-09-2015 |
Yin-Pin Chang, Zhubei City TW
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20120327232 | Automobile Equipment Control System and Control Method Thereof - An automobile equipment control system and a control method thereof. The system comprises an input module, a storage module, an image capturing module, a first recognizing module, a second recognizing module and a processing module. The input module is used to input a plurality of vehicle equipment setting values. The storage module is used to save a plurality of facial characteristic values and a plurality of setting values of vehicle equipment. The image capturing module is used to capture the image of the user. The first recognizing module analyzes the facial image in the image and extracts a facial characteristic point from the facial image. The second recognizing module analyzes the user's hand gesture, the user's head gestures or what the user speaks so as to decide which setting value of vehicle equipment is adopted to control the vehicle equipment. | 12-27-2012 |
20130022236 | Apparatus Capable of Detecting Location of Object Contained in Image Data and Detection Method Thereof - An apparatus capable of detecting location of object contained in image data and its detecting method are disclosed. The apparatus comprises an image capturing module, a weight assignment module, and a processing module. The image capturing module is for capturing an image. The weight assignment module performs the pixel weight/probability assignment according to the priori information and the image, and figures out the initial gravity center of the object according to the object location initialization. The processing module performs the statistical analysis according to the result of the pixel weight/probability assignment and the initial gravity center of the object so as to obtain the analysis result and update the object location. The processing module determines whether or not the analysis result meets the preset value, if it does, the processing module outputs an estimated result; if it doesn't, the processing module repeats the foregoing processes. | 01-24-2013 |
Yi-Ting Chang, Zhubei City TW
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20130044609 | APPARATUSES AND METHODS FOR ENHANCING DATA RATE FOR PACKET-SWITCHED (PS) DATA SERVICE - A wireless communication device for eliminating performance degradation of a packet-switched (PS) data service. The device comprises a processor configured to receive a request to perform the PS data service with a first subscriber identity card, reduce a plurality of scheduled monitoring tasks associated with a second subscriber identity card, and perform the PS data service with the first subscriber identity card while using the reduced plurality of scheduled monitoring tasks to maintain mobility or receive network messages with the second subscriber identity card. | 02-21-2013 |
Yuan-Hsun Chang, Zhubei City TW
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20130271198 | CLOCK GENERATION METHOD AND SYSTEM - The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock. | 10-17-2013 |
20140043082 | CLOCK GENERATION METHOD AND SYSTEM - The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock. | 02-13-2014 |
Yuan-Shun Chang, Zhubei City TW
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20150340433 | Power Semiconductor Device of Stripe Cell Geometry - A power semiconductor device of stripe cell geometry including a substrate, a plurality of striped power semiconductor units, and a guard ring structure is provided. The substrate has an active area and a termination area surrounding the active area defined thereon. The striped semiconductor unit includes a striped gate conductive structure. The striped semiconductor units are located in the active area. The guard ring structure is located in the termination area and includes at least a ring-shaped conductive structure surrounding the striped power semiconductor units. The ring-shaped conductive structure and the striped gate conductive structures are formed on the same conductive layer, and at least one of the striped gate conductive structures is separated from the nearby ring-shaped conductive structure and electrically connected to the nearby ring-shaped conductive structure through the gate metal pad. | 11-26-2015 |
Yu-Jung Chang, Zhubei City TW
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20140151751 | DENSITY GRADIENT CELL ARRAY - One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy region. For example, the array of cells includes an array of gates and an array of OD regions. In some embodiments, the array of gates includes a first set of gates associated with a first gate dimension and a second set of gates associated with a second gate dimension. In some embodiments, the array of OD regions includes a first set of OD regions associated with a first OD dimension and a second set of OD regions associated with a second OD dimension. In this manner, at least one of a pattern density, gate density, or OD density is customized to a region associated with active cells, thus mitigating density gradients between respective regions. | 06-05-2014 |
20160035615 | Methods Of Manufacturing A Semiconductor Device - Methods of manufacturing a semiconductor device are described. In an embodiment, the method may include providing a substrate having a metal layer disposed thereon, the metal layer having a conductive trace pattern formed therein; depositing a dielectric material over the conductive trace pattern of the metal layer; determining a layout of a plurality of air gaps that will be formed in the dielectric material based on a design rule checking (DRC) procedure and the conductive trace pattern; and forming the plurality of air gaps in the dielectric material based on the layout of the plurality of air gaps. | 02-04-2016 |
Yung-Cheng Chang, Zhubei City TW
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20130001722 | Co-implant for Backside Illumination Sensor - A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region. | 01-03-2013 |
20130082342 | POLISHING PROCESS FOR ENHANCING IMAGE QUALITY OF BACKSIDE ILLUMINATED IMAGE SENSOR - The present disclosure provides an image sensor device and a method of forming the image sensor device. In an example, a method includes providing a substrate having a first surface and a second surface, the first surface being opposite the second surface; forming a light sensing region at the first surface of the substrate; forming a doped layer at the second surface of the substrate; and after forming the doped layer, polishing the second surface of the substrate. | 04-04-2013 |
20130084660 | PROCESS FOR ENHANCING IMAGE QUALITY OF BACKSIDE ILLUMINATED IMAGE SENSOR - A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate. | 04-04-2013 |
20130119500 | IMAGE SENSOR WITH IMPROVED DARK CURRENT PERFORMANCE - Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon nitride. The image sensor device includes a metal shield formed on the compressively-stressed layer. The metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a second compressively-stressed layer formed on the metal shield and the first compressively-stressed layer. The second compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the second compressively-stressed layer. | 05-16-2013 |
20130134542 | DARK CURRENT REDUCTION FOR BACK SIDE ILLUMINATED IMAGE SENSOR - Provided is a semiconductor image sensor device that includes a non-scribe-line region and a scribe-line region. The image sensor device includes a first substrate portion disposed in the non-scribe-line region. The first substrate portion contains a doped radiation-sensing region. The image sensor device includes a second substrate portion disposed in the scribe-line region. The second substrate portion has the same material composition as the first substrate portion. Also provided is a method of fabricating an image sensor device. The method includes forming a plurality of radiation-sensing regions in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. The method includes forming an opening in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The method includes filling the opening with an organic material. | 05-30-2013 |
20130249037 | Co-implant for Backside Illumination Sensor - A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region. | 09-26-2013 |
20140197513 | Image Sensor with Improved Dark Current Performance - Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon nitride. The image sensor device includes a metal shield formed on the compressively-stressed layer. The metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a second compressively-stressed layer formed on the metal shield and the first compressively-stressed layer. The second compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the second compressively-stressed layer. | 07-17-2014 |
20140357010 | Process For Enhancing Image Quality Of Backside Illuminated Image Sensor - A method includes providing a substrate having a first surface and a second surface, the first surface being opposite the second surface, forming a light sensing region at the first surface of the substrate, forming a doped layer at the second surface of the substrate using a laser annealing process, and performing a chemical mechanical polishing process on the annealed, doped layer. | 12-04-2014 |
20150349009 | DARK CURRENT REDUCTION FOR BACK SIDE ILLUMINATED IMAGE SENSOR - A method of fabricating a semiconductor image sensor device is disclosed. A plurality of radiation-sensing regions is formed in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. An opening is formed in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The opening is then filled with an organic material. | 12-03-2015 |
Yu-Ru Chang, Zhubei City TW
Patent application number | Description | Published |
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20130221542 | Functional Spacer for SIP and Methods for Forming the Same - A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess. | 08-29-2013 |