Patent application number | Description | Published |
20140218381 | IMAGE ACCESS METHOD AND IMAGE ACCESS APPARATUS - An image access method applicable to an image access device is provided. The method includes: providing a plurality of codes that respectively represent a plurality of image sources; determining a plurality of sets of access settings according to a pixel format arrangement, each set of access setting corresponding to a code arrangement combination composed of the codes; and sequentially accessing data of the image sources by the image access apparatus according to the code arrangement combinations corresponding to the access settings. | 08-07-2014 |
20140340413 | LAYER ACCESS METHOD, DATA ACCESS DEVICE AND LAYER ACCESS ARRANGEMENT METHOD - A data access method is provided. The data access method is applied for a data device access device to access data from N layers to display an image, where N is a positive integer. Each of the N layers includes a horizontal start point, a horizontal end point, a vertical start point and a vertical end point. The data access method includes: dividing the image into a plurality of regions according to the horizontal start points, the horizontal end points, the vertical start points and the vertical end points, wherein the regions respectively correspond to the N layers; and accessing data from the respective layers corresponding to the regions when displaying the image. | 11-20-2014 |
20150186749 | IMAGE PROCESSING CIRCUIT AND METHOD THEREOF - An image processing method is provided. The method is for calculating a first weighted sum of absolute difference (WSAD) of a first search window and a corresponding first target window, and a second WSAD of a second search window and a corresponding second target window. The first and second search windows have a common matching window, and the first and second target windows have a common target block. The method includes: a) calculating a plurality of absolute differences of the common matching window and the common target block; b) determining a first weight coefficient group and a second weight coefficient group; and c) summing up products of multiplying the absolute differences by the first weight coefficient group to generate the first WSAD, and summing up products of multiplying the absolute differences by the second weight coefficient group to generate the second WSAD. | 07-02-2015 |
Patent application number | Description | Published |
20140167614 | ARC CHAMBER WITH MULTIPLE CATHODES FOR AN ION SOURCE - An apparatus for extending the useful life of an ion source, comprising an arc chamber containing a plurality of cathodes to be used sequentially and a plurality of repellers to protect cathodes when not in use. The arc chamber includes an arc chamber housing defining a reaction cavity, gas injection openings, a plurality of cathodes, and at least one repeller element. A method for extending the useful life of an ion source includes providing power to a first cathode of an arc chamber in an ion source, operating the first cathode, detecting a failure or degradation in performance of the first cathode, energizing a second cathode, and continuing operation of the arc chamber with the second cathode. | 06-19-2014 |
20150130353 | ARC CHAMBER WITH MULTIPLE CATHODES FOR AN ION SOURCE - An apparatus for extending the useful life of an ion source, comprising an arc chamber containing a plurality of cathodes to be used sequentially and a plurality of repellers to protect cathodes when not in use. The arc chamber includes an arc chamber housing defining a reaction cavity, gas injection openings, a plurality of cathodes, and at least one repeller element. A method for extending the useful life of an ion source includes providing power to a first cathode of an arc chamber in an ion source, operating the first cathode, detecting a failure or degradation in performance of the first cathode, energizing a second cathode, and continuing operation of the arc chamber with the second cathode. | 05-14-2015 |
Patent application number | Description | Published |
20110084370 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 04-14-2011 |
20110169150 | Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof - A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity. | 07-14-2011 |
20140021636 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 01-23-2014 |
20140151876 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 06-05-2014 |
20140346670 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 11-27-2014 |
Patent application number | Description | Published |
20140340836 | Modular USB Flash Drives with Replaceable Housings - A USB flash drive, comprising a housing comprising internal walls defining a receiving space, at least one of the internal walls having an engagement component, a memory main body disposed in the receiving space and comprising a hook slot component, and a fastener disposed in the receiving space comprising a protrusion component and a hook component, the hook component engaged with the hook slot component of the memory main body, and the protrusion component engaged with the engagement component of the housing, thereby fastening the memory main body to the housing. | 11-20-2014 |
20160081213 | Modular USB Flash Drives With Replaceable Housings - A USB flash drive, comprising a housing comprising internal walls defining a receiving space, at least one of the internal walls having an engagement component, a memory main body disposed in the receiving space and comprising a hook slot component, and a fastener disposed in the receiving space comprising a protrusion component and a hook component, the hook component engaged with the hook slot component of the memory main body, and the protrusion component engaged with the engagement component of the housing, thereby fastening the memory main body to the housing. | 03-17-2016 |