Patent application number | Description | Published |
20080258949 | Digital background correction of nonlinear error ADC's - The invention provides circuits and methods for estimating and correcting nonlinear error in analog to digital converters that is introduced by nonlinear circuit elements, for example one or more residue amplifiers in a pipelined analog to digital converter integrated circuit. In a preferred method of the invention, pseudo random calibration sequences are introduced into the digital signal to be converted by a flash digital to analog converter in one or more initial stages of the pipelined analog to digital converter circuit. A digital residue signal of the output of the one or more initial pipelined analog to digital converter stages is sampled. Intermodulation products of the pseudo random calibration sequences that are present in the digital residue signal are determined to estimate nonlinear error introduced by the residue amplifier in the one or more stages. A digital correction signal is provided to the output of the one or more stages to cancel estimated nonlinear error. | 10-23-2008 |
20100039182 | ADAPTIVE NOISE CANCELLATION FOR FRACTIONAL-N PHASE LOCKED LOOP - An embodiment of the invention is a circuit for adaptive phase noise cancellation for a fractional-N PLL. A preferred embodiment employs a split loop filter architecture. Two loop filter halves separately drive half-sized parallel varactors in a voltage controlled oscillator (VCO) and also drive a differential-input lowpass frequency selective circuit, e.g., a differential-input integrator in a least mean squared (LMS) feedback loop. The output of the differential-input lowpass frequency selective circuit controls the gain matching of a phase noise cancellation path to minimize phase noise arising from quantization error associated with the sequence of divider modulus values in the fractional-N PLL. The two varactor capacitances add together in the VCO tank, so the VCO frequency depends on the common-mode loop filter voltage and is relatively insensitive to differential-mode voltage. In contrast, the differential integrator operates on the differential-mode voltage from the two loop filter halves but attenuates their common-mode voltage. | 02-18-2010 |
20100166084 | NONLINEARITY ROBUST SUCCESSIVE REQUANTIZER - An embodiment of the invention is a successive requantizer, which serves as a replacement for a ΔΣ modulator in a fractional-N PLL or a DAC, and avoids the above-mentioned spurious tone problem, thereby circumventing the tradeoffs that result from reliance on common approach of making highly linear analog circuitry to avoid spurious tones. A successive requantizer fractional-N PLL of the invention has the potential to reduce power consumption and the cost of commercial communication devices. A successive requantizer of the invention performs digital quantization one bit at a time in such a way that the quantization noise can be engineered to have desirable properties such as non-linearity robustness. The invention is applicable to most high-performance digital communication systems, such as cellular telephone handsets and wireless local and metropolitan area network transceivers. | 07-01-2010 |
20120194369 | RING OSCILLATOR DELTA SIGMA ADC MODULATOR WITH REPLICA PATH NONLINEARITY CALIBRATION - An embodiment provides a continuous-time delta-sigma modulator for analog-to-digital conversion. The modulator includes a signal path generating including a ring voltage controlled oscillator driven by an analog input signal. The signal path produces digital values by sampling the ring voltage controlled oscillator. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects the digital values based upon determined nonlinear distortion coefficients. Preferred embodiment ADC ΔΣ modulators do not require any analog integrators, feedback DACs, comparators, or reference voltages, and do not require a low jitter clock. | 08-02-2012 |
20140368366 | MOSTLY-DIGITAL OPEN-LOOP RING OSCILLATOR DELTA-SIGMA ADC AND METHODS FOR CONVERSION - A continuous-time delta-sigma modulator for analog-to-digital conversion includes a pair of pseudo-differential signal paths including a pair of pseudo-differential signal paths including current-controlled ring oscillators as the load of open-loop common-source amplifiers that are driven by an analog input signal. The signal path produces digital values by sampling the open-loop current-controlled ring oscillators. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects digital values based upon the nonlinear distortion coefficients | 12-18-2014 |
20150035611 | VCO WITH LINEAR GAIN OVER A VERY WIDE TUNING RANGE - An oscillating circuit with linear gain is presented. The oscillating circuit may include a relaxation oscillator and a current compensation block. The relaxation oscillator includes a capacitor, a pair of resistors operative to deliver a first current to the capacitor, and a first current source adapted to generate the first current having a first predefined level. The current compensation block includes a second current source, and a pair of cross-coupled transistors coupled to the second current source and adapted to steer a current exceeding the first predefined level in the relaxation oscillator away from the capacitor and to the second current source. The proposed oscillating circuit generates an output signal which has a linear gain over a wide tuning range. | 02-05-2015 |
20160065223 | FOREGROUND AND BACKGROUND BANDWIDTH CALIBRATION TECHNIQUES FOR PHASE-LOCKED LOOPS - Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device. | 03-03-2016 |