Ku, Gyeonggi-Do
Bo Sung Ku, Gyeonggi-Do KR
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20120309649 | CELL CHIP AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a cell chip and a method for manufacturing the same. The cell chip may include: a substrate; and a first contact member disposed on the substrate, wherein a top end of the first contact member is provided with a first inclined contact surface inclined with respect to the substrate. | 12-06-2012 |
Han-Jun Ku, Gyeonggi-Do KR
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20130346923 | APPARATUS AND METHOD FOR DISPLAYING MENU IN MOBILE DEVICE - Disclosed is a method and apparatus for displaying a menu in a mobile device. An object generating event is detected for at least one selected menu item icon of at least one menu displayed on a touch screen. When the object generating event is detected, an object is generated and displayed, which performs an equivalent function to that of the at least one selected menu item icon. | 12-26-2013 |
20140055399 | METHOD AND APPARATUS FOR PROVIDING USER INTERFACE - A method of providing a user interface of a portable terminal includes receiving a mode switching request into a handwriting input mode from a user during executing an application, switching into the handwriting input mode according to the mode switching request, recognizing handwritten data received from the user, converting the recognized handwritten data to data with a preset format, processing the converted data through a preset scheme and displaying a result of the processing on a touch screen. | 02-27-2014 |
Hyo Sun Ku, Gyeonggi-Do KR
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20110045874 | MOBILE DEVICE HAVING ACOUSTIC SHOCK PREVENTION CIRCUIT AND RELATED OPERATION METHOD - A mobile device has an acoustic shock prevention circuit and prevents an acoustic shock unexpectedly occurring when receiver signals and speaker signals are output through a receiver-integrated speaker. The acoustic shock prevention circuit is preferably disposed between the receiver-integrated speaker and an audio processing unit is enabled in a receiver mode and disabled in a speaker mode. When the audio processing unit outputs audio signals partly exceeding a given output range, the enabled acoustic shock prevention circuit removes the exceeded parts of the audio signals. | 02-24-2011 |
Hyun-Ok Ku, Gyeonggi-Do KR
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20110275525 | Human Intestinal Normal Bacterial Flora DNA Chip and Method for Estimating Harmness to Human Body Due to Change of Human Intestinal Normal Bacterial Flora Using DNA Chip - The present invention relates to a DNA chip showing specific responses to a human intestinal normal bacterial flora and a method for estimating harmness to the human bodies due to the change of the human intestinal normal bacterial flora using the DNA chip. | 11-10-2011 |
20120165223 | Human Intestinal Normal Bacterial Flora DNA Chip and Method for Estimating Harmness to Human Body Due to Change of Human Intestinal Normal Bacterial Flora Using DNA Chip - The present invention relates to a DNA chip showing specific responses to a human intestinal normal bacterial flora and a method for estimating harmness to the human bodies due to the change of the human intestinal normal bacterial flora using the DNA chip. | 06-28-2012 |
Ja Chun Ku, Gyeonggi-Do KR
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20080214018 | TEMPLATE DERIVATIVE FOR FORMING ULTRA-LOW DIELECTRIC LAYER AND METHOD OF FORMING ULTRA-LOW DIELECTRIC LAYER USING THE SAME - A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer. | 09-04-2008 |
20090035917 | METHOD FOR FORMING DEVICE ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE USING ANNEALING STEPS TO ANNEAL FLOWABLE INSULATION LAYER - A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern. | 02-05-2009 |
20090061622 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING LIFTING OF AMORPHOUS CARBON LAYER FOR HARD MASK - In a method for manufacturing a semiconductor device, a conductive layer is formed on a semiconductor substrate. A surface of the conductive layer is then treated by plasma. After the conductive layer is treated, an amorphous carbon layer for a hard mask is formed on the surface of the conductive layer that has been treated by the plasma. | 03-05-2009 |
20090162990 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING THE DECREASE OF THE WIDTH OF AN ACTIVE REGION - A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate. | 06-25-2009 |
20100193901 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer. | 08-05-2010 |
20100261355 | METHOD FOR FORMING A HIGH QUALITY INSULATION LAYER ON A SEMICONDUCTOR DEVICE - A method for forming a high quality insulation layer on a semiconductor device is presented. The method includes a first step of supplying any one of a silicon source gas and an oxygen source gas into a process chamber in which a semiconductor substrate is placed; a second step of simultaneously supplying the silicon source gas and the oxygen source gas into the process chamber having undergone the first step and depositing a silicon oxide layer on the semiconductor substrate; and a third step of supplying any one of the silicon source gas and the oxygen source gas into the process chamber having undergone the second step. | 10-14-2010 |
20110143477 | METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING A CROSS PATTERNING TECHNIQUE - A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns. | 06-16-2011 |
20120231634 | TEMPLATE DERIVATIVE FOR FORMING ULTRA-LOW DIELECTRIC LAYER AND METHOD OF FORMING ULTRA-LOW DIELECTRIC LAYER USING THE SAME - A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer. | 09-13-2012 |
20120231635 | TEMPLATE DERIVATIVE FOR FORMING ULTRA-LOW DIELECTRIC LAYER AND METHOD OF FORMING ULTRA-LOW DIELECTRIC LAYER USING THE SAME - A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer. | 09-13-2012 |
20130336042 | RESISTIVE MEMORY DEVICE AND MEMORY APPARATUS AND DATA PROCESSING SYSTEM HAVING THE SAME - A resistive memory device operable with low power consumption and a memory apparatus and data processing system including the same are provided. The resistive memory includes a chalcogenide compound containing 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te). | 12-19-2013 |
20140256125 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer. | 09-11-2014 |
Jaesung Ku, Gyeonggi-Do KR
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20140282234 | APPLICATIONS PRESENTATION METHOD AND SYSTEM OF MOBILE TERMINAL - An applications presentation method and system is provided, the method and system including displaying, a map on a display when a map application is executed, the map scaled to a location range, searching via a processor for installed applications having location information corresponding to the location range among a plurality of applications stored in the mobile terminal, transmitting information identifying at least the location range and the installed applications to an application provision server, receiving information on non-installed applications having the location information corresponding to the location range from the application provision server, and displaying icons including icons of the installed applications and icons of the non-installed applications on the map. | 09-18-2014 |
Jae Sung Ku, Gyeonggi-Do KR
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20150046846 | APPARATUS AND METHOD FOR SHARING INFORMATION IN TERMINAL - An apparatus and a method for sharing information in a terminal are disclosed. At least one application is selected and sharing information including an icon and an identifier associated with the selected application is generated. The generated sharing information is transmitted to at least another terminal. | 02-12-2015 |
Ja-Hum Ku, Gyeonggi-Do KR
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20080242015 | Methods of Forming CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein and Circuits Formed Thereby - Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor. | 10-02-2008 |
20090124093 | Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities - A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors. | 05-14-2009 |
20090194817 | CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein - Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor. | 08-06-2009 |
Ja-Nam Ku, Gyeonggi-Do KR
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20090219142 | RFID SYSTEM AND METHOD OF TRANSMITTING LARGE DATA OF PASSIVE RFID - Provided are a radio frequency identification (RFID) system including an RFID reading apparatus and a passive RFID tag and a method of transferring and/or processing data using the same. An RFID reading apparatus includes a data input unit which receives data to be transferred to a passive RFID tag, a control unit which generates a transmission packet containing the data and a command directing data transfer, and a communication unit which converts the generated transmission packet into an RF signal and transfers the converted RF signal to the passive RFID tag. | 09-03-2009 |
Jeong Ku, Gyeonggi-Do KR
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20080274949 | Formulation of Albumin-Free Erythropoietin - Disclosed is a stable pharmaceutical solution preparation of erythropoietin (EPO), which includes a stabilizing agent not containing a blood-derived protein, thereby maintaining EPO activity for a prolonged period of time without the risk of viral contamination. The stable solution preparation further includes a non-ionic surfactant and a tonicity agent, thereby preventing EPO loss during storage and facilitating administration to the body. | 11-06-2008 |
Jong-Seok Ku, Gyeonggi-Do KR
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20140316136 | NOVEL ORGANIC ELECTROLUMINESCENCE COMPOUNDS AND ORGANIC ELECTROLUMINESCENCE DEVICE COMPRISING SAME - The present invention relates to novel organic electroluminescence compounds and an organic electroluminescence device comprising the same. The organic electroluminescence compound according to the present invention has an advantage of manufacturing an OLED device having long operating lifespan due to its high luminous efficiency compared with conventional materials, and having reduced power consumption induced by improved power efficiency. | 10-23-2014 |
20140323723 | NOVEL ORGANIC ELECTROLUMINESCENT COMPOUNDS AND AN ORGANIC ELECTROLUMINESCENT DEVICE USINC THE SAME - The present invention relates to a novel organic electroluminescent compound and an organic electroluminescent device containing the same. The organic electroluminescent compound according to the present invention has an advantage of manufacturing an OLED device having long operating lifespan due to its excellent lifespan characteristics, lower driving voltages, high luminous efficiency, and reduced power consumption induced by improved power efficiency. | 10-30-2014 |
Kie-Bong Ku, Gyeonggi-Do KR
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20110080794 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device allows a read command to be inputted thereto after a passage of a relatively short time period from a point in time where a write command has been inputted thereto. A method of operating the semiconductor memory device includes inputting a write command, inputting a read command in a preset period of time after the write command has been inputted, loading read data of a memory cell onto a data bus in response to the read command; and loading write data from outside of the semiconductor memory device onto the data bus in response to the write command. | 04-07-2011 |
20120153984 | METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICE - A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing. | 06-21-2012 |
20120163098 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MODE REGISTER SET AND METHOD FOR OPERATING THE SAME - A semiconductor memory device and method for operating the same includes a controller configured to generate a data buffer control signal in a mode register set (MRS) mode, a data buffer configured to buffer and output a plurality of MRS codes inputted through a data pad in response to the data buffer control signal, and a plurality of MRS command generators configured to receive the MRS codes outputted from the data buffer through a data line and generate a plurality of MRS commands based on the received MRS codes. | 06-28-2012 |
20120284590 | MONITORING DEVICE OF INTEGRATED CIRCUIT - A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode. | 11-08-2012 |
20130339641 | INTEGRATED CIRCUIT CHIP AND MEMORY DEVICE - A memory device includes a pad that provides an interface with an exterior, a first setting unit that generates a termination setting signal for setting the pad for a purpose of termination data strobe using a first specific code of a mode register set operation, a second setting unit that generates a mask setting signal for setting the pad for a purpose of data mask using a second specific code of the mode register set operation, and a third setting unit that generates a write inversion setting signal for setting the pad for a purpose of write data bus inversion using third specific code of the mode register set operation. When a setting signal with a higher priority is activated, a setting signal with a lower priority is deactivated regardless of a value of the corresponding code. | 12-19-2013 |
20140003170 | INTEGRATED CIRCUIT CHIP AND MEMORY DEVICE | 01-02-2014 |
20140003173 | CELL ARRAY AND MEMORY DEVICE INCLUDING THE SAME | 01-02-2014 |
20140133247 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor memory device includes a compression unit configured to compress a plurality of data, which are read from a memory cell region based on successive read commands and addresses, and to successively output the compressed data during a first test mode, a latching unit configured to latch the compressed data in response to a read strobe signal and to fix the latched value when a fail is detected from the compressed data during the first test mode, and an output unit configured to output the latched value to the outside during a second test mode. | 05-15-2014 |
20150016201 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode. | 01-15-2015 |
20150071009 | SEMICONDUCTOR DEVICE - A semiconductor device includes a data bus inversion (DBI) decision unit suitable for deciding whether a DBI operation mode is performed, based on a read data, and generating a DBI decision signal corresponding to a result of the decision; an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision is reflected, in a DBI operation mode; a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized read data and inverted signals of the synchronized read data, in the DBI operation mode; and a data output unit suitable for selectively outputting the synchronized read data and the inverted signals of the synchronized read data, to an external in response to the DBI decision signal, the arrangement control signal and an output control signal, in the DBI operation mode. | 03-12-2015 |
20150084665 | METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICE - A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing. | 03-26-2015 |
20150084667 | METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICE - A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing. | 03-26-2015 |
Kyong I. Ku, Gyeonggi-Do KR
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20090328029 | SOFTWARE PORTAL SYSTEM FOR PROVIDING RELATION INFORMATION OF SOFTWARE AND DATA FORMAT AND METHOD OF OPERATING THE SAME - A software portal system for providing relation information of software and a data format, and a method of operating the same are provided. To provide software by downloading or service simultaneously with relation information between software and software, software and a data format, and data formats, the software portal system includes a relation information management unit and a web service providing unit. The relation information system defines a relation of software and a data format to constitute and manage relation information of the software and the data format. The web service providing unit acquires and provides the relation information of the software managed by the relation information management unit when the software is provided by downloading or service, and acquires and provides the relation information of the data format managed by the relation information management unit when the relation information of the data format is inquired. Accordingly, a user can be provided with high quality of service. | 12-31-2009 |
Kyong-I Ku, Gyeonggi-Do JP
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20100017863 | PORTABLE STORAGE APPARATUS FOR PROVIDING WORKING ENVIRONMENT MIGRATION SERVICE AND METHOD THEREOF - Provided are an apparatus and method for providing a working environment migration service. The portable storage apparatus, includes: a management and execution unit for performing user authentication by connection to an external user terminal, managing a user profile and application information, and executing a context management unit; a working environment storage unit for storing an application context and data representing the working state at the time of log out; and the context management unit for recovering and executing the application context and data stored in the working environment storage unit upon execution by the management and execution unit, and collecting the application context and data representing the working state at the time of log out, and storing them in the working environment storage unit. | 01-21-2010 |
Mi-Na Ku, Gyeonggi-Do KR
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20120270395 | METHOD FOR FABRICATING METAL PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a metal pattern in a semiconductor device includes forming a metal layer over a substrate, forming a hard mask layer over the metal layer, forming a sacrifice pattern over the hard mask layer, forming a spacer pattern on sidewalks of the sacrifice pattern, removing the sacrifice pattern, forming a hard mask pattern by etching the hard mask layer using the spacer pattern as an etch barrier, forming an etching protection layer over the hard mask pattern and on sidewalks of the hard mask pattern, and forming the metal pattern by performing primary and secondary etching processes on the metal layer using the etching protection layer as an etch barrier. | 10-25-2012 |
20130122703 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an etch target layer including an insulation layer and a metal layer over a substrate, forming a hard mask layer pattern over the etch target layer, forming a protective layer pattern which includes a region having a shape of an overhang formed in an upper portion of the hard mask layer pattern, etching the insulation layer of the etch target layer by using the first region as an etch barrier, and etching the metal layer of the etch target layer by using the second region as an etch barrier. | 05-16-2013 |
Sae Kwang Ku, Gyeonggi-Do KR
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20080200526 | Composition for the Prevention and Treatment of Allergic Inflammatory Disease - Disclosed herein is a composition for the treatment and prevention of allergic inflammatory diseases comprising N-hydroxy-4-{5-[4-(5-isopropyl-2-methyl-1,3-thiazol-4-yl)phenoxy]pentoxy}-benzamidine, 4-{5-[4-(5-isopropyl-2-methyl-1,3-thiazol-4-yl)phenoxy]pentoxy}-benzamidine or pharmaceutically acceptable salts. The composition exhibits excellent medicinal effects on allergic inflammatory diseases, with a great reduction in typical chronic inflammation symptoms, such as an increase of eosinophil level in bronchoalveolar lavage fluid, total leukocyte level and eosinophil level in blood, the hypertrophy or hyperplasia of bronchial epithelium due to an increase in the number of mucus cells, a reduction in alveolar surface area resulting from the hyptertrophy of alveolar walls, and the infiltration of inflammatory cells. | 08-21-2008 |
20080287509 | Pharmaceutical Composition for the Treatment of Bone Fracture - Disclosed herein is a composition for the treatment bone fracture comprising N-hydroxy-4-{5-[4-(5-isopropyl-2-methyl-1,3-thiazol-4-yl)phenoxy]pentoxyl-benzamidine, 4-{5-[4-(5-isopropyl-2-methyl-1,3-thiazol-4-yl)phenoxy]pentoxy}-benzamidine or pharmaceutically acceptable salts thereof as a medicinally effective ingredient. The composition of the present invention can significantly reduce the volume of bony callus, and increase bony density and strength of bony callus, and decrease the contents of connective tissue and cartilage tissue in bony callus, and thus promote loss and ossification of the bony callus formed during the fracture healing process. Therefore, the composition of the present invention is useful for the treatment of bone fracture. | 11-20-2008 |
20090054642 | NOVEL BENZAMIDINE DERIVATIVE, PROCESS FOR THE PREPARATION THEREOF AND PHARMACEUTICAL COMPOSITION COMPRISING SAME - The present invention relates to a novel benzamidine derivative, a process for the preparation thereof, and a pharmaceutical composition comprising the same. The benzamidine derivative of the present invention effectively inhibits osteoclast differentiation at an extremely low concentration, and greatly increases the trabecular bone volume, and thus it can be advantageously used for the prevention and treatment of osteoporosis. | 02-26-2009 |
20100240890 | Novel benzamidine derivatives, process for the preparation thereof and pharmaceutical composition comprising the same - The present invention relates to novel benzamidine derivatives, process for the preparation thereof and pharmaceutical composition comprising the same. The novel benzamidine derivatives of the present invention are useful for the prevention and treatment of osteoporosis, bone fractures and allergic inflammatory diseases. | 09-23-2010 |
Sang-Chul Ku, Gyeonggi-Do KR
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20130217410 | METHOD AND APPARATUS FOR POSITIONING LOCATION OF WIRELESS ACCESS POINT - A wireless access point location positioning method and terminal operation method for floor information update. A method includes a terminal acquiring absolute location information, and transmitting surrounding Access Point (AP) signal information of an absolute location, together with the absolute location information, to a location server. The location server includes receiving surrounding AP signal information of the absolute location and associated atmospheric pressure information thereof, together with the absolute location information, from a terminal, determining locations of APs based on the received absolute location information and the surrounding AP signal information of the absolute location, and updating a related AP location using the determined locations of the APs. | 08-22-2013 |
20130219437 | MULTIMEDIA SERVICE SYSTEM AND METHOD FOR OPERATING THE SAME - A multimedia service system includes a portable terminal that communicates with a server. When a portable terminal is located at or within a building, the portable terminal acquires floor information of the building from a server, calculates a present altitude itself, determines a floor corresponding to the calculated altitude from the floor information, receives a multimedia service for the detected floor from the server, and outputs the received multimedia service. The server provides altitude-by-altitude floor information of the building and a floor-by-floor multimedia service to the portable terminal. | 08-22-2013 |
Soung-Min Ku, Gyeonggi-Do KR
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20100055861 | METHOD FOR FABRICATING CAPACITOR IN SEMICONDUCTOR DEVICE - A method for fabricating a capacitor in a semiconductor device includes forming an insulation layer over a substrate, forming a storage node contact plug passing through the insulation layer and coupled to the substrate, recessing the storage node contact plug to a certain depth to obtain a sloped profile, forming a barrier metal over the surface profile of the recessed storage node contact plug, forming a sacrificial layer over the substrate structure, etching the sacrificial layer to form an opening exposing the barrier metal, forming a bottom electrode over the surface profile of the opening, and removing the etched sacrificial layer. | 03-04-2010 |
Sunju Ku, Gyeonggi-Do KR
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20120097514 | TOUCH SCREEN PANEL AND METHOD OF MANUFACTURING THE SAME - A touch screen panel includes a substrate, a first touch electrode layer including first touch electrodes formed to be divided on regions defined as a pad part, a routing part, and a channel bridge part on the substrate, a soluble insulator layer including soluble insulators formed so as to expose portions of the first touch electrodes, and a second touch electrode layer formed on the soluble insulator layer. | 04-26-2012 |
Sun-Ju Ku, Gyeonggi-Do KR
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20140168554 | ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE INCLUDING THE SAME - An array substrate includes a substrate; gate lines over the substrate along a first direction; data lines over the substrate along a second direction and crossing the gate lines to define pixel regions; a thin film transistor at each crossing portion of the gate and data lines; an insulating layer covering the thin film transistor and having a flat top surface; a common electrode on the insulating layer all over the substrate; a common line on the common electrode; a passivation layer on the common line; and a pixel electrode on the passivation layer in each pixel region and connected to the thin film transistor, the pixel electrode including electrode patterns, wherein the passivation layer has a step height at a top surface of the passivation layer due to the plurality of common lines. | 06-19-2014 |
Tae-Hung Ku, Gyeonggi-Do KR
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20080284186 | Pick and Place Apparatus - A pick and place apparatus includes a 1 | 11-20-2008 |
20080298946 | Test Handler - A test handler is disclosed, which comprises a test tray, at least one opening unit, and a position changing apparatus. The test tray aligns a plurality of inserts on its side. Each insert loads at least one semiconductor device thereon. The opening unit opens inserts at one part of the one side of the test tray. The position changing apparatus moves at least one opening unit in such a way that the at least one opening units can be located at another part of the one side of the test tray, such that the at least one opening units can open inserts at said another part of the one side of the test tray. The present invention can reduce the number of replaced parts according to change in the semiconductor device size, production cost, and part replacement time. Also, the present invention can be easily applied to various types of testers. | 12-04-2008 |