Patent application number | Description | Published |
20100244220 | LAYOUT STRUCTURE AND METHOD OF DIE - A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally. | 09-30-2010 |
20100289139 | HARDWIRED SWITCH OF DIE STACK AND OPERATING METHOD OF HARDWIRED SWITCH - A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided. | 11-18-2010 |
20100295189 | METHOD FOR REPAIRING CHIP AND STACKED STRUCTURE OF CHIPS - A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional. | 11-25-2010 |
20100320565 | WAFER AND METHOD FOR IMPROVING YIELD RATE OF WAFER - A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV. | 12-23-2010 |
20110080184 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
20110080185 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
20110304010 | ELECTROSTATIC DISCHARGE PROTECTION SCHEME FOR SEMICONDUCTOR DEVICE STACKING PROCESS - An electrostatic discharge (ESD) protection scheme for a semiconductor device stacking process is provided, in which an equivalent electrical resistance of a specific path is designed to be less than an equivalent electrical resistance of other paths. Accordingly, when a first active layer and a second active layer in the semiconductor device are stacked, by designing suitable ESD protection cells on such a specific path, electrical charges accumulated on the top layer wafer (or die) select such a specific path over the other paths to be released to the grounded bottom layer wafer (or die), so as to achieve an ESD protection effect. In addition, since such a specific path also serves as a heat dissipation path in a three dimensional integrated circuit (3D IC), an overall heat resistance of the 3D IC may be reduced to improve a heat dissipation effect. | 12-15-2011 |
20120146207 | STACKED STRUCTURE AND STACKED METHOD FOR THREE-DIMENSIONAL CHIP - A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip; stacking the function chip above the I/O chip; and stacking at least one memory chip between the function chip and the I/O chip. | 06-14-2012 |
20120193815 | STACKED STRUCTURE OF CHIPS - A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function. | 08-02-2012 |
20120231563 | OPERATING METHOD OF HARDWIRED SWITCH - An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die. | 09-13-2012 |
20130064026 | TECHNOLOGY OF MEMORY REPAIR AFTER STACKING OF THREE-DIMENSIONAL INTEGRATED CIRCUIT - A three-dimensional integrated circuit (3-D IC) includes a controller chip and at least one memory chip, in which, besides an original storage capacity, the memory chip further includes multiple spare memory cells and an address translation circuit with an external activation/enablement function. After the memory chip and the controller chip are stacked, the controller chip may still activate/enable a spare in the memory chip to repair a damaged or deteriorated memory cell in the memory chip through at least one vertical interconnect (for example, through-silicon via (TSV)), regardless of whether the damaged or deteriorated memory cell has been repaired or not before the controller chip and the memory chip are stacked. | 03-14-2013 |
20130159950 | METHOD AND APPARATUS OF AN INTEGRATED CIRCUIT - A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump | 06-20-2013 |
20130161819 | SEMICONDUCTOR DEVICE STACKED STRUCTURE - A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure. | 06-27-2013 |
20130283224 | METHOD AND APPARATUS OF AN INTEGRATED CIRCUIT - A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump. | 10-24-2013 |
20130293255 | METHOD FOR TESTING THROUGH-SILICON-VIA - A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range. | 11-07-2013 |
20140139259 | TEST METHOD FOR INTERPOSER - A test method for an interposer is provided. The interposer includes a plurality of conductive lines therein and a plurality of connecting contacts thereon, wherein the connecting contacts are electrically connected to the conductive lines. The test method for an interposer provides a passive transponder device. The passive transponder device includes a first circuit including an open/short test circuit and at least a pair of connecting contacts. The test method for an interposer includes contacting the connecting contacts of the first circuit in the passive transponder device with the selected contacts on the interposer to form a checking area and conducting an open-circuit or short-circuit test for the interposer through the checking area. | 05-22-2014 |
20140325311 | HYBRID ERROR CORRECTION METHOD AND MEMORY REPAIR APPARATUS THEREOF - A hybrid error correction method and a memory repair apparatus thereof are provided for a dynamic random access memory (DRAM). The memory repair apparatus includes a mode register and a hybrid error correction code and redundancy (HEAR) module. When the DRAM enters a standby mode, the mode register switches the DRAM to be controlled by the HEAR module. The HEAR module generates parity data of the error correction code within a default refresh period. The HEAR module extends the refresh period of the DRAM and uses the parity data for error detection to locate a data retention error in the DRAM until the maximum allowable refresh period supported by the HEAR module is reached. Before the DRAM returns to a working mode from a standby mode, the HEAR module performs an error correction process according to fail bit data and writes corrected data into the DRAM. | 10-30-2014 |
20150049569 | MEMORY DEVICE - A memory device including at least one bit-line decoding circuit, at least one word-line decoding circuit, a plurality of memory blocks, and a plurality of switches is provided. The sizes of the plurality of memory blocks include at least one first size and a second size, and the first size is greater than the second size. The plurality of memory blocks with the first size are grouped as at least one first group, and the plurality of memory blocks with the second size are grouped as at least one second group. Compared to the first group, the second group is closer to the bit-line decoding circuit and/or the word-line decoding circuit. The switches are controlled by at least one control signal, so as to enable or disable the first group and/or the second group. | 02-19-2015 |