Tobias Werner
Tobias Werner, Weil Im Schoenbuch DE
Patent application number | Description | Published |
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20080258769 | Tri-State Circuit Element Plus Tri-State-Multiplexer Circuitry - A Tri-State circuit element ( | 10-23-2008 |
20080301616 | Layout Generator for Routing and Designing an LSI - According to the present invention an automated layout generator is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route. | 12-04-2008 |
20100302895 | ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK GENERATION - A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals. | 12-02-2010 |
20140192602 | DEFECTIVE MEMORY COLUMN REPLACEMENT WITH LOAD ISOLATION - Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells. | 07-10-2014 |
Tobias Werner, Boeblingen DE
Patent application number | Description | Published |
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20110310680 | Interleave Memory Array Arrangement - A memory array includes a plurality of memory cells, wherein each cell of the plurality of memory cells is defined by a row and a column, wherein each row includes a unique identifying address, and wherein each column is associated with one of two sets, the columns arranged such that a column associated with a first set is adjacent to a column of a second set. | 12-22-2011 |
20120005643 | System and Method for Placing Integrated Circuit Functional Blocks According to Dataflow Width - Macroblock placement for an integrated circuit register-transfer level design is enhanced by tagging blocks having a set of functions as usage element definitions that have a minimum input signal width, such as tags added to a netlist of the design. Tagged blocks aid preferred and regular placement of library cells that are morphed to adapt for reduced congestion and improved utilization. | 01-05-2012 |
Tobias Werner, Weil Im Schoenicher DE
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20110317478 | Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through Capability - An improved method for performing a write through operation during a write operation of a SRAM cell ( | 12-29-2011 |
Tobias Werner, Fellbach DE
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20130200731 | METHOD AND DEVICE FOR DISCHARGING AN INTERMEDIATE CIRCUIT OF A POWER SUPPLY NETWORK - The present invention relates to a method ( | 08-08-2013 |
20140084830 | CONTROL DEVICE AND METHOD FOR OPERATING AN ELECTRICAL MACHINE DRIVEN BY AN INVERTER - The invention relates to a method for operating an electrical machine ( | 03-27-2014 |
Tobias Werner, Schoenbuch DE
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20140130004 | INTEGRATED CIRCUIT SCHEMATICS HAVING IMBEDDED SCALING INFORMATION FOR GENERATING A DESIGN INSTANCE - A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data. | 05-08-2014 |
20140254290 | Local Evaluation Circuit for Static Random-Access Memory - A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The second switch is configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal. The third switch is configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal. The fourth switch is configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal. | 09-11-2014 |