Patent application number | Description | Published |
20080258755 | Noise Reduction Among Conductors - Noise reduction among conductors, the conductors disposed adjacent to one another, the conductors characterized as two or more aggressor conductors and one or more victim conductors, a least two of the aggressor conductors driven with at least two signals that induce unwanted crosstalk upon at least one of the victim conductors, a programmable delay device disposed in a signal path of each of the at least two signals that induce unwanted crosstalk, including programming a delay period into each programmable delay device; receiving, simultaneously at the programmable delay devices, the at least two signals that induce unwanted crosstalk; and transmitting, on two aggressor conductors, the at least two signals that induce unwanted crosstalk, with the at least two signals separated in time by the delay period. | 10-23-2008 |
20080261451 | PRE-DISTORTION BASED IMPEDENCE DISCONTINUITY REMEDIATION FOR VIA STUBS AND CONNECTORS IN PRINTED CIRCUIT BOARD DESIGN - Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line. | 10-23-2008 |
20080301352 | BUS ARCHITECTURE - A system and method for implementing a bus. In one embodiment, the system includes a bus switch operative to couple to a bus, and a plurality of trace segments coupled to the bus switch, where the trace segments have different lengths. The bus switch is operative to connect one of the trace segments to the bus based on at least one system requirement, and the selected trace segment cancels signal reflections on the bus. | 12-04-2008 |
20080308293 | Cable For High Speed Data Communications - A cable for high speed data communications and methods for manufacturing such cable are disclosed, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The cable also includes conductive shield material wrapped in a rotational direction at a rate along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps of the conductive shield material along and about the longitudinal axis, the conductive shield material having a variable width. Transmitting signals on the cable including transmitting a balanced signal characterized by a frequency in the range of 7-9 gigahertz on the cable. | 12-18-2008 |
20090007048 | DESIGN STRUCTURE FOR A COMPUTER MEMORY SYSTEM WITH A SHARED MEMORY MODULE JUNCTION CONNECTOR - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory module system and DIMM connector is provided. A DIMM connector includes a plurality of DIMM sockets for receiving a corresponding plurality of DIMMs in a radially oriented, angularly spaced orientation. The DIMM sockets are connected in parallel at a memory module junction so that socket terminals of each DIMM socket are joined to the same relative terminal of all the other DIMM sockets along electronic pathways of substantially equal length. A memory controller selectively communicates with the DIMMs via the DIMM junction. By virtue of the improved topology, impedance within the DIMM connector may be better matched to minimize reflections and improve signal quality. | 01-01-2009 |
20090019204 | SELF-HEALING NOISE DISPERSION SYSTEM FOR HIGH PERFORMANCE MULTIDROP SYSTEMS - The key limiter in a multi-drop system, such as a multi-drop memory system, is the super-positioning of reflection noise from multiple modules or pluggable units, such as DIMMs. Using the noise cancellation approach of the present invention, the noise is distributed across the width of the pulse thus significantly reducing the impact of noise super-positioning. Use of the system of the present invention provides improved noise margins and is a key enabler of high performance, high speed bus, particularly at higher bit rates, as well as an enabler for higher capacity modules, such as DIMMs. The system provides for electrical traces from each of the modules of varying lengths thereby distributing the noise reflections. | 01-15-2009 |
20090021264 | METHOD AND APPARATUS FOR REPEATABLE DRIVE STRENGTH ASSESSMENTS OF HIGH SPEED MEMORY DIMMS - The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided. | 01-22-2009 |
20090030927 | METHOD AND APPARATUS FOR MANAGING ORGANIZATIONAL RESOURCES - A computer implemented method, apparatus, and computer program product for managing organizational resources. The process combines social group data with management information data to form social network data, wherein social group data is derived from interactions among a plurality of users of a social group. The process analyzes the social network data to identify associations among the plurality of users, and generates a multidimensional social network model using the associations among the plurality of users. Thereafter, the process presents a set of recommendations for allocation of the organizational resources, wherein the set of recommendations are derived from the social network model. | 01-29-2009 |
20090049339 | Programmable Diagnostic Memory Module - A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation. | 02-19-2009 |
20090049341 | Method for Performing Memory Diagnostics Using a Programmable Diagnostic Memory Module - A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation. | 02-19-2009 |
20090049414 | METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE - Reducing via stub resonance in printed circuit boards. In one aspect, a method for reducing via stub resonance in a circuit board includes determining that resonance exists for a signal to be transmitted through a signal via extending across a plurality of layers in the circuit board. The resonance is caused by a via stub of the signal via, the via stub extending past a layer connected to the signal via. A location is determined for a ground via to be placed relative to the signal via, the location of the ground via being determined based on reducing the resonance for the signal to be transmitted in the signal via. | 02-19-2009 |
20090079274 | Electromagnetic Morphing Apparatus for Hot Pluggable Architected Systems - In electronic devices with signal traces positioned between a ground layer and a voltage reference layer, systems and methods are provided for connecting a hot pluggable device to the electronic device in a manner that diminishes signal degradation due to parasitic effects. The first device has a second reference layer near the connector that connects to a second device voltage reference layer maintained at a given voltage level across the connector. In the first device near the connector the signal trace is positioned in between a ground layer of the first device and the second reference layer which is maintained at a given voltage by a voltage regulator of the second device. The signal return current travels past the second reference layer to a first reference layer of the first device which is maintained by the first device's voltage regulator through AC decoupling capacitors minimizing the current return path discontinuity. | 03-26-2009 |
20090079456 | APPARATUS, SYSTEM, AND METHOD FOR INTEGRATED COMPONENT TESTING - An apparatus, system, and method are disclosed for integrating component testing. A voltage module modifies a reference voltage integral to an electronic device to a plurality of reference voltage values. A test module tests a component of the electronic device at each of the plurality of reference voltage values. In addition, the test module determines a voltage range for the component, wherein the voltage range comprises voltage values between a high voltage failure and a low voltage failure. An optimization module sets the reference voltage value to within the voltage range. | 03-26-2009 |
20090090908 | Providing A Duplicate Test Signal Of An Output Signal Under Test In An Integrated Circuit - Providing a duplicate test signal of an output signal under test in an integrated circuit including selecting through a multiplexer an output signal under test, the output signal under test selected from a plurality of output signals of the integrated circuit; providing through the multiplexer a duplicate signal of the selected output signal under test; adding a high impedance load on the duplicate signal thereby reducing the amplitude of the duplicate signal; and amplifying the reduced duplicate signal thereby creating the duplicate test signal. | 04-09-2009 |
20090091345 | STRUCTURE FOR PROVIDING A DUPLICATE TEST SIGNAL OF AN OUTPUT SIGNAL UNDER TEST IN AN INTEGRATED CIRCUIT - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure provides a duplicate test signal of an output signal under test in an integrated circuit including selecting through a multiplexer an output signal under test, the output signal under test selected from a plurality of output signals of the integrated circuit; providing through the multiplexer a duplicate signal of the selected output signal under test; adding a high impedance load on the duplicate signal thereby reducing the amplitude of the duplicate signal; and amplifying the reduced duplicate signal thereby creating the duplicate test signal. | 04-09-2009 |
20090102487 | Method for Validating Printed Circuit Board Materials for High Speed Applications - A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe. | 04-23-2009 |
20090106976 | METHOD FOR REDUCING NOISE COUPLING IN HIGH SPEED DIGITAL SYSTEMS - Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer. | 04-30-2009 |
20090107705 | METHODS AND SYSTEMS FOR REDUCING NOISE COUPLING IN HIGH SPEED DIGITAL SYSTEMS - Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer. | 04-30-2009 |
20090144256 | Workflow control in a resource hierarchy - Illustrative embodiments provide a computer implemented method, an apparatus and a computer program product for workflow management control in a resource hierarchy. In one embodiment, the computer implemented method comprises, receiving data, from a plurality of target data sources, into a collection, and synthesizing the received data in the collection to establish a resource hierarchy. The collection is then queried, using criteria in a request for a resource from a requester to provide a selected resource from the collection, forming a response, the selected resource of the response being a best fit result, and returning the response to the requester. | 06-04-2009 |
20090166054 | Cable For High Speed Data Communications - A cable for high speed data communications and methods for manufacturing such cable are disclosed, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The cable also includes conductive shield material wrapped in a rotational direction at a rate along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps of the conductive shield material along and about the longitudinal axis, the conductive shield material having a variable width. Transmitting signals on the cable including transmitting a balanced signal characterized by a frequency in the range of 7-9 gigahertz on the cable. | 07-02-2009 |
20090168931 | METHOD AND APPARATUS FOR JITTER COMPENSATION IN RECEIVER CIRCUITS USING NONLINEAR DYNAMIC PHASE SHIFTING TECHNIQUE BASED ON BIT HISTORY PATTERN - The present invention provides a simple, easy to implement method and apparatus to reduce jitter in a channel and expand the eye width and eye height of the eye pattern of the signal. The method and apparatus of the present invention reduces jitter specific to a channel in a high speed interface. The present invention utilizes a phasing shifting mechanism based on history of the incoming bits at the receiver. The input bits from the channel are shifted in time before getting to the receiver. This approach significantly reduces Intersymbol Interference (ISI) and deterministic jitter, thus opening up the eye width and eye height for a given interface. | 07-02-2009 |
20090229850 | Cable For High Speed Data Communications - A cable for high speed data communications and methods for manufacturing such cable are disclosed, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The cable also includes conductive shield material wrapped in a rotational direction at a wrap rate along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps of the conductive shield material along and about the longitudinal axis, an inner surface of the conductive shield material roughened to reduce non-linear attenuation of signals transmitted through the conductive shield material. Transmitting signals on the cable including transmitting a balanced signal characterized by a frequency in the range of 7-9 gigahertz on the cable. | 09-17-2009 |
20090263768 | Generating An Optimized Analytical Business Transformation - A method, system, and computer program product for optimizing a Business Process Model (BPM) having at least one work process are presented. At a simulation client, a determination is made whether a simulated business outcome associated with a test BPM satisfies a business value deficiency associated with a current BPM. In response to a determination that the simulated business outcome does not satisfy the business value deficiency, the test BPM is optimized. Once the simulation client determines that the simulated business outcome satisfies the business value deficiency, the test BPM is implemented as an actual BPM. Moreover, an actual business outcome associated with the actual BPM is generated. A determination is made whether the actual business outcome satisfies the simulated business outcome. In response to a determination that the actual business outcome does not satisfy the simulated business outcome, the actual BPM is optimized. | 10-22-2009 |
20090292579 | Technical Support Routing Among Members Of A Technical Support Group - Computer-implemented methods, apparatus and products for technical support routing among members of a technical support group, including maintaining, by a configuration manager, a system configuration history of a user's computer system, the system configuration history including historical records of changes in configuration of the user's computer system; receiving, by a technical support module, a support request identifying a current error that occurred during operation of the user's computer system including receiving information describing the error and the system configuration history of the user's computer system; and routing, by the technical support module automatically without human intervention, the support request to one or more particular members of the technical support group in dependence upon the information describing the error and the system configuration history. | 11-26-2009 |
20090307636 | SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS - A method of optimizing a very large scale integrated circuit design takes a circuit description which includes interconnected circuit components and characteristic variables assigned to the circuit components such as environmental, operational or process parameters, computes a first solution for the characteristic variables using a statistical analysis, and then computes a second solution for the characteristic variables using an evolutionary analysis seeded by the first solution. In the exemplary implementation the statistical analysis is a central composite design (CCD) and the evolutionary analysis is a genetic algorithm. Best case and worst case CCD solutions may be used to seed separate genetic algorithm runs and derive global best case and global worst case solutions. These solutions may be compared for sensitivity analysis. The method thereby provides significant reduction in time-to-solution with accurate simulation results. | 12-10-2009 |
20090308649 | Printed Circuit Board With Reduced Signal Distortion - A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals. | 12-17-2009 |
20100014569 | Identifying An Optimized Test Bit Pattern For Analyzing Electrical Communications Channel Topologies - Identifying an optimized test bit pattern for analyzing electrical communications channel topologies, including: ranking according to channel quality, from worst to best, a set of channel topologies for an electrical communications channel; and for each ranked channel topology beginning with the worst, carrying out the following steps in an iterative loop until a concatenated test bit pattern and a previously optimized test bit pattern are functionally equally fit: concatenating to a previously optimized test bit pattern an additional test bit pattern; optimizing the concatenated test bit pattern values for a next ranked channel in the subset, leaving the optimized values of the previously optimized test bit pattern unchanged; and comparing through use of a fitness function the relative qualities of the previously optimized test bit pattern and the optimized concatenated test bit pattern. | 01-21-2010 |
20100057657 | INTELLIGENT PROBLEM TRACKING ELECTRONIC SYSTEM FOR OPTIMIZING TECHNICAL SUPPORT - Embodiments of the present invention address deficiencies of the art in respect to technical support management and provide a novel and non-obvious method, system and computer program product for intelligent problem tracking to optimize technical support. In an embodiment of the invention, a method for intelligent problem tracking can include receiving recorded information of tracked end user behavior collected in an end user computing system while the end user addresses a problem in the end user computing system, determining a level of technical sophistication of the user based upon the recorded information, selecting a technical support level corresponding to the determined level of technical sophistication of the user, and transmitting a resolution to the problem in a message to the end user computing system commensurate with the selected technical support level. | 03-04-2010 |
20100060527 | ELECTROMAGNETIC BAND GAP TUNING USING UNDULATING BRANCHES - Embodiments of the invention include electromagnetic band gap (EBG) structures having undulating branches to tune the resulting stopband. A periodically patterned structure of conductive patches are interconnected by the undulating branches. Physical parameters of the undulating branches, such as the number of undulations or “turns” per branch, may be selected to tune the stopband in an effort to achieve a target stopband. Accordingly, embodiments of the invention also include methods of designing and manufacturing an EBG structure using undulating branches. | 03-11-2010 |
20100073893 | MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE - Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer. | 03-25-2010 |
20100099219 | MITIGATION OF PLATING STUB RESONANCE BY CONTROLLING SURFACE ROUGHNESS - Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations. | 04-22-2010 |
20100100412 | WORKFLOW MANAGEMENT IN A GLOBAL SUPPORT ORGANIZATION - Customer support involves multiple levels of support, where customer support personnel at higher levels have more experience and a higher cost associated with their services. A random assignment of support personnel to a problem, at lower levels, can lead to multiple call transfers, a customer being put “on hold”, ineffective resource utilization, and high service costs being billed to customers. Functionality can be implemented to assign a support person to resolve the customer's problem based on a multi-dimensional dynamic social network database of resources (e.g., personnel experience, success rate, skill set, social network, etc.) which allows for efficient assignment of support personnel to a problem. Routing a customer call to the most appropriate support person at a given level before determining support personnel at higher levels can ensure optimization in terms of return on investment and resource utilization. Optimally selecting and assigning support personnel can also ensure customer satisfaction. | 04-22-2010 |
20100108350 | Cable For High Speed Data Communications - Cables and methods of manufacturing cables for high speed data communications, the cable including: a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers parallel with and along a longitudinal axis; and folded conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps along and about the longitudinal axis, the conductive shield material comprising a first conductive layer and second conductive layer separated by an inner-shield dielectric layer. | 05-06-2010 |
20100118019 | Dynamically Managing Power Consumption Of A Computer With Graphics Adapter Configurations - Dynamically managing power consumption of a computer, the computer including two or more graphics adapters, the computer having a number of graphics adapter configurations including one or more of the graphics adapters, where managing power consumption includes: monitoring, by a graphics driver, operation of a current graphics adapter configuration, the operation characterized by a graphics processing load; determining, in dependence upon the graphics processing load, whether operation of the current graphics adapter configuration conforms to predefined graphics processing criteria; if operation conforms, processing graphics, by the graphics adapter, for display with the one or more graphics adapters of the current graphics adapter configuration; and if operation does not conform, processing graphics, by the graphics adapter, for display with the one or more graphics adapters of another graphics adapter configuration. | 05-13-2010 |
20100138677 | OPTIMIZATION OF DATA DISTRIBUTION AND POWER CONSUMPTION IN A DATA CENTER - The distribution of data among a plurality of data storage devices may be optimized, in one embodiment, by redistributing the data to move less-active data to lesser performing data storage devices and to move more-active data to higher performing data storage devices. Power consumption in the datacenter may be optimized by selectively reducing power to data storage devices to which less-active data, such as persistent data, has been moved. | 06-03-2010 |
20100229131 | SWARM INTELLIGENCE FOR ELECTRICAL DESIGN SPACE MODELING AND OPTIMIZATION - A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned. | 09-09-2010 |
20100231209 | Testing An Electrical Component - Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters. | 09-16-2010 |
20100252358 | Airflow Optimization and Noise Reduction in Computer Systems - In one embodiment, a fan is used to generate airflow through a computer chassis to a fan air inlet. An audible frequency component of the airflow is identified and selected. A sound wave is generated having a generated frequency equal to the selected audible frequency component of the airflow. The generated sound wave is introduced into the airflow with the generated frequency out of phase with the audible frequency component of the airflow. The magnitude of the generated frequency may be selected as a function of fan speed and/or air sensed pressure within the airflow. The frequency, phase, and magnitude of the generated sound wave may be selected and enforced by a baseboard management controller. | 10-07-2010 |
20100294557 | Transmission Cable with Spirally Wrapped Shielding - Embodiments of the invention are directed to transmission cables, and particularly to twinax cables, for transmitting digital data and other information between components in a data processing environment. One embodiment of the invention is directed to an information transmission cable that comprises first and second signal carrying conductors of specified length, each of the signal carrying conductors being disposed to carry information signals and having a longitudinal axis. The embodiment further includes an insulating structure comprising an amount of specified dielectric insulation material, the insulating structure being positioned to surround the first and second signal carrying conductors along their respective lengths, and acting to maintain the first and second signal conductors in spaced apart parallel relationship with each other. A first drain conductor is positioned proximate to the first signal carrying conductor in spaced apart parallel relationship, and is further positioned in a first prespecified relationship with a reference line that intersects the respective longitudinal axes of the first and second signal carrying conductors, and that lies in a plane orthogonal thereto. In similar manner, a second drain conductor is positioned proximate to the second signal carrying conductor in spaced apart parallel relationship, and is further positioned in a second prespecified relationship with the reference line. Shielding material is spirally wrapped around the first and second signaling conductors, the first and second drain conductors and the insulating structure. | 11-25-2010 |
20110061898 | REDUCING CROSS-TALK IN HIGH SPEED CERAMIC PACKAGES USING SELECTIVELY-WIDENED MESH - One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package. | 03-17-2011 |
20110073359 | Through-Hole-Vias In Multi-Layer Printed Circuit Boards - Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper. | 03-31-2011 |
20110103030 | Packages and Methods for Mitigating Plating Stub Effects - Packages and methods for mitigating plating stub effects. The semiconductor package includes an interposer substrate having a first side, a second side, a peripheral edge connecting the first side with the second side, a signal line on the first side, and an electrode pad on the first side. A semiconductor element is mounted on the first side of the interposer substrate. The semiconductor element is connected with the electrode pad by the signal line. A terminating resistor is mounted on the interposer substrate. A plating stub, which is located on the interposer substrate, has a first end portion that terminates near the peripheral edge of the interposer substrate and a second end portion that is electrically connected to the electrode. The first end portion is electrically connected through the terminating resistor to an electrical ground. | 05-05-2011 |
20110127062 | Cable For High Speed Data Communications - A cables for high speed data communications, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The first inner conductor is substantially parallel to the second inner conductor and to a longitudinal axis. The cable includes a conductive shield wrapped around the first and second inner conductors, with an overlap of the conductive shield along and about the longitudinal axis. The overlap is aligned with a low current plane. The low current plane substantially parallel to the first and second inner conductors, substantially equidistant from the first and second inner conductors, and substantially orthogonal to a plane including the first and second inner conductors. | 06-02-2011 |
20110133326 | Reducing Plating Stub Reflections in a Chip Package Using Resistive Coupling - Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer. | 06-09-2011 |
20110140709 | LOCATING SHORT CIRCUITS IN PRINTED CIRCUIT BOARDS - One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit. | 06-16-2011 |
20110149740 | RECEIVER SIGNAL PROBING USING A SHARED PROBE POINT - A device and method are disclosed wherein a receiver signal line within an integrated circuit may be selected for probing. In one embodiment, a plurality of signal pads and a test pad are provided on an external surface of an integrated circuit chip. A plurality of signal lines extends through the integrated circuit chip to the signal pads. A multiplexer on the integrated circuit chip is configured for individually selecting any of the signal lines. An amplifier on the integrated circuit chip amplifies a selected signal and communicates the amplified signal to an externally-accessible test pad to be probed. | 06-23-2011 |
20110161055 | SPACE SOLUTION SEARCH - A statistical approach can be used to efficiently supply an initial population that provides a good global description of a design space. The SI based simulation can then find a global best design within a reduced number of simulations. The statistical approach can be utilized to determine a plurality of potential best and worst case designs from a design space. The plurality of potential best and worst case designs from the design space seed or prime a SI based simulation. The best case designs are based on design parameters than can be controlled. The worst case designs are based on design parameters than cannot be controlled due. SI based simulations can then be run on the best case designs with respect to the worst case designs to determine probability of failure of the best case design. | 06-30-2011 |
20110267906 | Measuring SDRAM Control Signal Timing - Measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’), including combining into a trigger signal for an oscilloscope display control signals of an SDRAM under test, the control signals derived only from a single type of memory operations; and driving, continually during both READ and WRITE operations to and from the SDRAM under test, the oscilloscope display with a memory bus data signal (‘DQ’) and a memory bus clock signal (‘DQS’) from the SDRAM under test. | 11-03-2011 |
20110289463 | ELECTRICAL DESIGN SPACE EXPLORATION - A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach. | 11-24-2011 |
20110303445 | Printed Circuit Board With Reduced Dielectric Loss - A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB. | 12-15-2011 |
20120004930 | Managing and Providing Healthcare Services - A method, computer program product, and apparatus for managing healthcare services are provided. A processor unit receives medical information about a patient. The processor unit generates a group of providers containing a number of providers based on the medical information received about the patient. A number of matches from the number of providers are identified for the patient using the number of providers and based on a number of criteria. | 01-05-2012 |
20120032330 | MITIGATION OF PLATING STUB RESONANCE BY CONTROLLING SURFACE ROUGHNESS - Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations. | 02-09-2012 |
20120167033 | Controlling Plating Stub Reflections In A Chip Package - Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. Embodiments include determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount; based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width for an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate; and generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width. | 06-28-2012 |
20120185294 | GENERATING AN OPTIMIZED ANALYTICAL BUSINESS TRANSFORMATION - Techniques for optimizing a Business Process Model (BPM) having at least one work process are presented. At a simulation client, a determination is made whether a simulated business outcome associated with a test BPM satisfies a business value deficiency associated with a current BPM. In response to a determination that the simulated business outcome does not satisfy the business value deficiency, the test BPM is optimized. Once the simulation client determines that the simulated business outcome satisfies the business value deficiency, the test BPM is implemented as an actual BPM. Moreover, an actual business outcome associated with the actual BPM is generated. A determination is made whether the actual business outcome satisfies the simulated business outcome. In response to a determination that the actual business outcome does not satisfy the simulated business outcome, the actual BPM is optimized. | 07-19-2012 |
20120193135 | Through-Hole-Vias In Multi-Layer Printed Circuit Boards - Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper. | 08-02-2012 |
20120200346 | Through-Hole-Vias In Multi-Layer Printed Circuit Boards - Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper. | 08-09-2012 |
20120327622 | PRE-DISTORTION BASED IMPEDENCE DISCONTINUITY REMEDIATION FOR VIA STUBS AND CONNECTORS IN PRINTED CIRCUIT BOARD DESIGN - Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line. | 12-27-2012 |
20130025119 | Printed Circuit Board With Reduced Dielectric Loss - A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB. | 01-31-2013 |
20140123489 | THROUGH-HOLE-VIAS IN MULTI-LAYER PRINTED CIRCUIT BOARDS - Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of manufacturing a PCB. Embodiments include depositing upon layers of laminate printed circuit traces and joining the layers of laminate. Embodiments also include drilling at least one via hole through the layers of laminate and placing in the via hole a via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a second metal having a conductivity lower than the conductivity of copper. | 05-08-2014 |
20140284217 | MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE - The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency. | 09-25-2014 |