Patent application number | Description | Published |
20080258754 | SECURITY ELEMENT FOR AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT INCLUDING THE SAME, AND METHOD FOR SECURING AN INTEGRATED CIRCUIT - An integrated circuit including a substrate; a circuit pattern formed over the substrate; and one or more fences formed around edges of the circuit pattern, each of the one or more fences having a determined electrical resistance which is used to detect the addition of malicious circuitry. Each fence has a determined electrical resistance which is used to monitor the validity of the fence. | 10-23-2008 |
20080261126 | SECURE PHOTOMASK WITH BLOCKING APERTURE - A secure photomask including a substrate having one or more pattern layers formed thereon and a blocking aperture disposed below the one or more pattern layers that prevents at least one of unauthorized use and copying of the photomask. | 10-23-2008 |
20080261127 | PHOTOMASK WITH DETECTOR FOR OPTIMIZING AN INTEGRATED CIRCUIT PRODUCTION PROCESS AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT USING THE SAME - A photomask for integrated circuit production for development of integrated circuit components, where the integrated circuit production uses a radiation source that generates a source image, includes a substrate with one or more layers disposed thereon; a source separator element that separates the source image into one or more duplicate source images; one or more polarizing elements each corresponding to one of the one or more duplicate source images; and one or more sensors each corresponding to one of the one or more polarizing elements, the one or more sensors sensing one or more radiation characteristics of the radiation source. | 10-23-2008 |
20100129736 | Photomask Having A Reduced Field Size And Method Of Using The Same - A photomask used for manufacturing a semiconductor device includes a substrate; and one or more layers disposed over the substrate, the one or more layers defining a full field area and a reduced field area with a primary pattern being formed in the reduced field area, wherein the full field area is defined by a width of at least 90 mm and a height of at least 100 mm, and the reduced field area is defined by a width within the range of approximately 20-80 mm and a height within the range of approximately 20-80 mm. | 05-27-2010 |
20110086511 | PHOTOMASK HAVING A REDUCED FIELD SIZE AND METHOD OF USING THE SAME - A photomask used for manufacturing a semiconductor device includes a substrate; and one or more layers disposed over the substrate, the one or more layers defining a full field area and a reduced field area with a primary pattern being formed in the reduced field area, wherein the full field area is defined by a width of at least 90 mm and a height of at least 100 mm, and the reduced field area is defined by a width within the range of approximately 20-80 mm and a height within the range of approximately 20-80 mm, a center point of the primary patterned area being spaced a predetermined distance from a center point of the photomask so that the primary patterned area avoids photomask defects. | 04-14-2011 |
20140204450 | MICROFLUIDIC THERMOPTIC ENERGY PROCESSOR - A microfluidic panel including at least one substrate, one or more channels formed in the substrate, and fluid disposed within the one or more channels. The fluid is selected to store thermal energy and the microfluidic panel is adapted to convert the thermal energy into useable energy or condition the energy to adjust optical wavelength passband of the panel. | 07-24-2014 |