Patent application number | Description | Published |
20080235668 | OPERATING SYSTEM SUPPORT FOR THREAD-LEVEL BREAKPOINTS - A computer implemented method, apparatus, and computer usable program code for processing breakpoints. A breakpoint is detected during execution of a process. A thread that is currently executing is identified as an identified thread. A determination is made as to whether the breakpoint is applicable to the identified thread. In response to the determination that the breakpoint is applicable to the identified thread, the execution of the process is halted. Execution of the process continues without halting execution of the process if the breakpoint is inapplicable to the identified thread. | 09-25-2008 |
20090024706 | GRANULARLY SELECTING A SUBSET OF RECIPIENTS WHO CAN REPLY TO A SENDER'S E-MAIL - A method, system, and computer program product for assigning reply status to an outgoing electronic mail (e-mail) message. While creating an e-mail message, an interface is provided for granularly assigning or denying reply privileges to recipients of an outgoing e-mail message. Reply status is assigned by selecting a subset of recipients by name, e-mail address, and/or e-mail group who may reply to the e-mail. As the recipient's reply status is modified, the outgoing e-mail is updated, revising the reply e-mail address for each recipient. When the recipient is granted reply status, the e-mail address of the original sender is provided as the reply e-mail address. However, in the event the recipient is not granted reply status, the e-mail address of an automated, unmanned e-mail account is provided as the reply e-mail address. | 01-22-2009 |
20090037703 | CONDITIONAL DATA WATCHPOINT MANAGEMENT - A method, system and computer program product for managing a conditional data watchpoint in a set of instructions being traced is shown in accordance with illustrative embodiments. In one particular embodiment, the method comprises initializing a conditional data watchpoint and determining the watchpoint has been encountered. Upon that determination, examining a current instruction context associated with the encountered watchpoint prior to completion of the current instruction execution, further determining a first action responsive to a positive context examination; otherwise, determining a second action. | 02-05-2009 |
20090276756 | Method To Apply Persistence To Selected Attributes Of Static And Dynamic Operating System Components - A process for managing customizations for components in a component tree includes for each customization associated with the parent of a component, matching the pathname of the component with the customization path. The process further includes associating the customization with the component, if the matching results in a partial match. The process further includes applying the customization to the component, if the matching results in a complete match. | 11-05-2009 |
20090313610 | Advisory warning and workaround indications to user when stopped between load and store conditional instructions while using source level debuggers - A load store advisory program sets a breakpoint within a portion of a program, determines if the breakpoint will cause unexpected behavior, and generates a warning if it is determined that the breakpoint will cause unexpected behavior. The unexpected behavior may be the result of setting a breakpoint within a load-store sequence that, because of the breakpoint, will repeatedly fail. | 12-17-2009 |
20100174946 | Method for Debugging a Hang Condition in a Process Without Affecting the Process State - Embodiments of the invention are associated with an application process that comprises multiple threads, wherein threads of the process are disposes to run on a data processing system, and each thread can have a user mode or a kernel mode machine state, or both, selectively, when it is running. An embodiment directed to a method comprises the steps of allocating a specified memory location for each of the threads, and responsive to a given thread entering a sleep state, selectively saving the kernel mode machine state of the given thread in the specified memory location for the given thread. The saved machine state comprises the state of the given thread immediately prior to the given thread entering the sleep state. In response to detecting a hang condition in the operation of the process, a debugger is attached to the process to access at least one of the saved user mode machine states. The method further includes analyzing information provided by the at least one accessed machine state to determine the cause of the hang condition, and restoring the original state upon detachment, so the debugger attachment is completely transparent to the target process. | 07-08-2010 |
20100251239 | Component Lock Tracing - Methods, systems, and products for lock tracing at a component level. The method includes associating one or more locks with a component of the operating system; initiating lock tracing for the component; and instrumenting the component-associated locks with lock tracing program instructions in response to initiating lock tracing. The locks are selected from a group of locks configured for use by an operating system and individually comprise locking code. The component lock tracing may be static or dynamic. | 09-30-2010 |
20100287279 | Ensuring Affinity at All Affinity Domains by Folding at Each Affinity Level Possible for a Partition Spanning Multiple Nodes - The different illustrative embodiments provide a method, apparatus, and computer program product for folding at each affinity level for a partition spanning multiple nodes. In one illustrative embodiment, a method is provided for identifying a number of domains in a number of affinity levels. A lightest loaded domain is identified in the number of domains identified. A number of nodes are identified in the lightest loaded domain identified. A lightest loaded node is identified in the number of nodes. A lightest loaded processing unit on the lightest loaded node is identified and the lightest loaded processing unit is folded. | 11-11-2010 |
20100333087 | Allocation and Regulation of CPU Entitlement for Virtual Processors in Logical Partitioned Platform - A system, method, and computer program product for managing processor entitlement of virtual processors in logical partitioned data processing system. One embodiment of the invention provides a method of managing processing resources in a data processing system. The method involves creating a resource set comprising a grouping of virtual processors, and allocating a processing resource entitlement the resource set. The method also includes assigning the resource set to a workload, receiving a request by the workload for utilization of processing resources, and in response to receiving the workload request dispatching the assigned resource set. The method further includes determining whether the dispatched virtual processors of the resource set have exceeded the assigned processing resource entitlement, and in response to determining that the processing resource entitlement has been exceeded, undispatching the resource set. | 12-30-2010 |
20110022803 | Two Partition Accelerator and Application of Tiered Flash to Cache Hierarchy in Partition Acceleration - An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map. | 01-27-2011 |
20110022895 | Software Component Self-Scrubbing - Software components “self-scrub” to improve software reliability, serviceability and availability (RAS). Each component designates a routine to perform a component level consistency check on major data structures and to verify the state of component. This is performed as an on-going task during the life of the component. The component registers an entry point with the system to receive notification of scrubbing parameter changes. The entry point is also called with the request to perform component-scrubbing operations. The entry point functions are responsible for executing within limitations on central processing unit (CPU) usage and memory footprint when performing scrubbing operations. | 01-27-2011 |
20110072418 | TRACING MEMORY UPDATE FOR DEBUGGING COMPUTER PROGRAM - A system, method, and computer program product for expediting the identification of computer program code that is the source of errors in the execution of a computer program. A debugger monitors a specified memory address, or group of addresses for updates, during execution of the computer program. In response to determining that a running computer program has updated the memory address, the processor executes a watchpoint handler to identify the source of errors in a computer program executing in a data processing system. The watchpoint handler gathers trace information associated with the faulty processing thread, and records the trace information to a memory location. The watchpoint handler may also apply filters to the trace information to identify the source of the error, saving valuable debugging time. | 03-24-2011 |
20110153949 | DELAYED REPLACEMENT OF CACHE ENTRIES - A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that should be protected from replacement (e.g., a large page entry), the cache entry replacement unit can determine a second replacement entry. The cache entry replacement unit can “skip” the first replacement entry by replacing the second replacement entry with a new entry, if the second replacement entry is an entry that should not be protected (e.g., a small page entry). The first replacement entry can be skipped a predefined number of times before the first replacement entry is replaced with a new entry. | 06-23-2011 |
20110320573 | APPLICATION SERVER FOR MAINFRAME COMPUTER SYSTEMS - A method, apparatus, and computer program product for running software on an adapter. In response to a connection of a hardware interface for the adapter with a current host computer, a processor unit in the adapter determines whether a set of protocols for communicating with the current host computer to access resources is present on the adapter. In response to the set of protocols being absent on the adapter, the processor unit obtains the set of protocols from the current host computer. The processor unit identifies a set of available resources in the current host computer for use by the adapter using the set of protocols. The processor unit runs software stored on a set of storage devices in the adapter using the set of available resources identified for use by the adapter. | 12-29-2011 |
20120042131 | Flexible use of extended cache using a partition cache footprint - An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core. | 02-16-2012 |
20120060012 | MANAGEMENT OF LOW-PAGING SPACE CONDITIONS IN AN OPERATING SYSTEM - A virtual memory management unit can implement various techniques for managing paging space. The virtual memory management unit can monitor a number of unallocated large sized pages and can determine when the number of unallocated large sized pages drops below a page threshold. Unallocated contiguous smaller-sized pages can be aggregated to obtain unallocated larger-sized pages, which can then be allocated to processes as required to improve efficiency of disk I/O operations. Allocated smaller-sized pages can also be reorganized to obtain the unallocated contiguous smaller-sized pages that can then be aggregated to yield the larger-sized pages. Furthermore, content can also be compressed before being written to the paging space to reduce the number of pages that are to be allocated to processes. This can enable efficient management of the paging space without terminating processes. | 03-08-2012 |
20120110274 | Operating System Image Management - In a data processing system including multiple logical partitions (LPARs), an application executes on a first logical partition (LPAR) of the multiple LPARs, where the application uses a first operation system stored in a first memory partition of a shared pool memory of the data processing system. A virtualization management component (a) initiates an update process that quiesces operations of the first LPAR, (b) pages in, via a virtual input/output server coupled to a first paging device, a first image of a second operating system from the first paging device to the shared pool memory; (c) changes one or more pointers associated with the application to point to one or more portions of the second operating system, such that the application uses the second operating system, when resumed; and (b) resumes execution the application. | 05-03-2012 |
20120185860 | Component Lock Tracing - Methods for lock tracing at a component level. The method includes associating one or more locks with a component of the operating system; initiating lock tracing for the component; and instrumenting the component-associated locks with lock tracing program instructions in response to initiating lock tracing. The locks are selected from a group of locks configured for use by an operating system and individually comprise locking code. The component lock tracing may be static or dynamic. | 07-19-2012 |
20120191859 | Ensuring Affinity at All Affinity Domains by Folding at Each Affinity Level Possible for a Partition Spanning Multiple Nodes - The different illustrative embodiments provide a method, apparatus, and computer program product for folding at each affinity level for a partition spanning multiple nodes. In one illustrative embodiment, a method is provided for identifying a number of domains in a number of affinity levels. A lightest loaded domain is identified in the number of domains identified. A number of nodes are identified in the lightest loaded domain identified. A lightest loaded node is identified in the number of nodes. A lightest loaded processing unit on the lightest loaded node is identified and the lightest loaded processing unit is folded. | 07-26-2012 |
20120246652 | Processor Management Via Thread Status - Various systems, processes, and products may be used to manage a processor. In particular implementations, managing a processor may include the ability to determine whether a thread is pausing for a short period of time and place a wait event for the thread in a queue based on a short thread pause occurring. Managing a processor may also include the ability to activate a delay thread that determines whether a wait time associated with the pause has expired and remove the wait event from the queue based on the wait time having expired. | 09-27-2012 |
20120311605 | PROCESSOR CORE POWER MANAGEMENT TAKING INTO ACCOUNT THREAD LOCK CONTENTION - A method maintains, for each processing element in a processor, a count of threads waiting in a data structure for hand-off locks in order to execute on the processing element. The method maintains the processing element in a first power state if the count of threads waiting for hand-off locks is greater than zero. The method puts the processing element in a second power state if the count of threads waiting for hand-off locks is equal to zero and no thread is ready to be processed by the processing element. The method returns the processing element to the first power state if the count of threads becomes greater than zero, or if a thread becomes ready to be processed by the processing element. | 12-06-2012 |
20130166873 | MANAGEMENT OF LOW-PAGING SPACE CONDITIONS IN AN OPERATING SYSTEM - A virtual memory management unit can implement various techniques for managing paging space. The virtual memory management unit can monitor a number of unallocated large sized pages and can determine when the number of unallocated large sized pages drops below a page threshold. Unallocated contiguous smaller-sized pages can be aggregated to obtain unallocated larger-sized pages, which can then be allocated to processes as required to improve efficiency of disk I/O operations. Allocated smaller-sized pages can also be reorganized to obtain the unallocated contiguous smaller-sized pages that can then be aggregated to yield the larger-sized pages. Furthermore, content can also be compressed before being written to the paging space to reduce the number of pages that are to be allocated to processes. This can enable efficient management of the paging space without terminating processes. | 06-27-2013 |
20130254490 | DELAYED REPLACEMENT OF TLB ENTRIES - A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that should be protected from replacement (e.g., a large page entry), the cache entry replacement unit can determine a second replacement entry. The cache entry replacement unit can “skip” the first replacement entry by replacing the second replacement entry with a new entry, if the second replacement entry is an entry that should not be protected (e.g., a small page entry). The first replacement entry can be skipped a predefined number of times before the first replacement entry is replaced with a new entry. | 09-26-2013 |
20130254775 | EFFICIENT LOCK HAND-OFF IN A SYMMETRIC MULTIPROCESSING SYSTEM - Provided are techniques for providing a first lock, corresponding to a resource, in a memory that is global to a plurality of processor; spinning, by a first thread running on a first processor of the processors, at a low hardware-thread priority on the first lock such that the first processor does not yield processor cycles to a hypervisor; spinning, by a second thread running on a second processor, on a second lock in a memory local to the second processor such that the second processor is configured to yield processor cycles to the hypervisor; acquiring the lock and the corresponding resource by the first thread; and, in response to the acquiring of the lock by the first thread, spinning, by the second thread, at the low hardware-thread priority on the first lock rather than the second lock such that the second processor does not yield processor cycles to the hypervisor. | 09-26-2013 |
20140101662 | EFFICIENT LOCK HAND-OFF IN A SYMMETRIC MULTIPROCESSOR SYSTEM - Provided are techniques for providing a first lock, corresponding to a resource, in a memory that is global to a plurality of processor; spinning, by a first thread running on a first processor of the processors, at a low hardware-thread priority on the first lock such that the first processor does not yield processor cycles to a hypervisor; spinning, by a second thread running on a second processor, on a second lock in a memory local to the second processor such that the second processor is configured to yield processor cycles to the hypervisor; acquiring the lock and the corresponding resource by the first thread; and, in response to the acquiring of the lock by the first thread, spinning, by the second thread, at the low hardware-thread priority on the first lock rather than the second lock such that the second processor does not yield processor cycles to the hypervisor. | 04-10-2014 |
20140173595 | HYBRID VIRTUAL MACHINE CONFIGURATION MANAGEMENT - A system and technique for hybrid virtual machine configuration management includes a processor and executable logic to: assign to a first set of virtual resources associated with a virtual machine a first priority, the first set associated with entitled resources for the virtual machine; assign to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; map the first set to a first physical resource of a pool of shared physical resources, the pool of shared physical resources allocatable to the first and second sets, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocate the first physical resource to the first set of virtual resources. | 06-19-2014 |
20140173597 | HYBRID VIRTUAL MACHINE CONFIGURATION MANAGEMENT - According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes: assigning to a first set of virtual resources associated with entitled resources of a virtual machine a first priority; assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; mapping the first set of virtual resources to a first physical resource of a pool of shared physical resources allocatable to the first and second sets of virtual resources, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocating the first physical resource to the first set of virtual resources. | 06-19-2014 |