Patent application number | Description | Published |
20160038550 | METHODS AND COMPOSITIONS FOR TREATING CONDITIONS ASSOCIATED WITH MEMORY LOSS - Methods and compositions are described for treating, preventing, ameliorating, or the like one or more symptoms associated with memory loss. Also described are pharmaceutical compositions including one or more of a monoamine oxidase inhibitor, a cyclooxygenase inhibitor, a nootropic agent, a terpene, a terpenoid, and a pharmaceutically acceptable carrier. | 02-11-2016 |
20160039591 | PACKAGING SYSTEMS, DEVICES, METHODS, AND COMPOSITION INCLUDING CANNABINOID UNIT DOSE FORMS - Systems, devices, methods, and compositions are described for providing, among other things, cannabinoid unit dose forms. Also described are packaging, systems, devices, methods, and compositions including, among other things, phyto-cannabinoid unit dose forms for treating various diseases or disorders. | 02-11-2016 |
Patent application number | Description | Published |
20100308402 | 3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES - Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described. | 12-09-2010 |
20120088331 | WAFER LEVEL STACK DIE PACKAGE - This document discusses, among other things, apparatus and methods for an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components. | 04-12-2012 |
20120267714 | DOUBLE LAYER METAL (DLM) POWER MOSFET - This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically. | 10-25-2012 |
Patent application number | Description | Published |
20080224211 | Monolithic MOSFET and Schottky diode device - A Schottky diode is integrated into a planar or trench topology MOSFET having parallel spaced source regions diffused into spaced base stripes. The diffusions forming the source and base stripes are interrupted to permit the drift region to extend to the top of the die and receive a Schottky barrier metal and the source contact. The MOSFET and Schottky share the same drift region, and the pitch between base and source stripes is not changed to receive the Schottky structure. | 09-18-2008 |
20080237632 | III-nitride power semiconductor device - A III-nitride power semiconductor device that includes a first III-nitride power semiconductor device and a second III-nitride power semiconductor device formed in a common semiconductor die and operatively integrated to form a half-bridge. | 10-02-2008 |
20090218617 | SUPERJUNCTION POWER SEMICONDUCTOR DEVICE - A superjunction power semiconductor device which includes spaced drift regions each extending from the bottom of a respective gate trench to the substrate of the device. | 09-03-2009 |
20100140689 | Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 06-10-2010 |
20100155839 | LATERAL MOSFET WITH SUBSTRATE DRAIN CONNECTION - In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body. | 06-24-2010 |
20100264490 | LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN - A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region. | 10-21-2010 |
20110171798 | LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN - A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region. | 07-14-2011 |
20120018803 | LATERAL DRAIN MOSFET WITH SUBSTRATE DRAIN CONNECTION - In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body. | 01-26-2012 |
20120043553 | Hybrid Semiconductor Device Having a GaN Transistor and a Silicon MOSFET - A hybrid device including a silicon based MOSFET operatively connected with a GaN based device. | 02-23-2012 |
20120248526 | Wafer Level MOSFET Metallization - Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance R | 10-04-2012 |
20130277735 | WAFER LEVEL MOSFET METALLIZATION - Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance R | 10-24-2013 |
20140042532 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 02-13-2014 |
20150194521 | TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS - Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. | 07-09-2015 |
Patent application number | Description | Published |
20100188022 | METHODS, LUMINAIRES AND SYSTEMS FOR MATCHING A COMPOSITE LIGHT SPECTRUM TO A TARGET LIGHT SPECTRUM - Methods, luminaires and systems for matching a composite light spectrum to a target light spectrum are disclosed. Method embodiments may be optimized for simultaneously maximizing luminous output with minimal chromaticity error. Method embodiments may further be optimized for simultaneously minimizing both chromaticity and spectral error. Embodiments of the present invention may be used with composite light sources having four or more distinct dominant colors within the visible spectrum. | 07-29-2010 |
20120140463 | LED PROFILE LUMINAIRE - A lighting fixture comprising a light source including an array of LEDs, a plurality of collimating optics, and a light-mixing assembly comprising a reflective tube having a converging section and a diverging section. The array comprises LEDs have a plurality of colors, such as at least one white LED and at least one amber LED positioned on a perimeter of the array. The reflective tube preferably includes a necked portion between the converging section and the diverging section. For example, a sidewall of the reflective tube can be longitudinally curved (e.g., in the shape of an asphere or a parabola). In one embodiment, a shape of the sidewall of the reflective tube can be adjustable to modify the light wash exiting the light-mixing assembly. | 06-07-2012 |
20130214704 | METHODS, LUMINAIRES AND SYSTEMS FOR MATCHING A COMPOSITE LIGHT SPECTRUM TO A TARGET LIGHT SPECTRUM - Methods, luminaires and systems for matching a composite light spectrum to a target light spectrum are disclosed. Method embodiments may be optimized for simultaneously maximizing luminous output with minimal chromaticity error. Method embodiments may further be optimized for simultaneously minimizing both chromaticity and spectral error. Embodiments of the present invention may be used with composite light sources having four or more distinct dominant colors within the visible spectrum. | 08-22-2013 |
Patent application number | Description | Published |
20080209848 | Method of constructing a modular load-bearing structural column - A practical method of manufacturing, assembling, and constructing a single silo or building or a cluster of polygonal storage silos using a column comprising horizontally-arrayed structural column panels. Column panels within a top horizontal array vertically aligning with column panels of a next lower horizontal array such that no discernible gap exists between top and bottom edges of column panels within the column. seams, where top and bottom edges of column panels meet, preferably occur in different horizontal planes from each other throughout the column, thereby creating a stagger or offset of column components in relationship to each other. Multiple layers of column components with the same, similar, or different configurations can be added to preferably cover seams of underlying column components to enhance structural integrity. A structure built with these columns can be constructed using a cost-effective and relatively safe method of lifting. In addition, three or more of these structural columns can be connected together with wall panels or beams to fashion a polygonal compartment or multiple polygonal compartments, to serve as structural support for heavy loads, as a process tower for supporting equipment, a multi-story building for human occupancy (such as an apartment complex), or as bulk storage silo(s). The column can join standard and customized beams and wall panels. The column can extend above a structure to support a tower or another level, or it can extend below to serve as a support column for the entire structure. Columns can be attached to wall panels of round structures, to serve as stiffeners, or to the sides of polygonal structures, to serve as side-wall supports. | 09-04-2008 |
Patent application number | Description | Published |
20110079317 | WATER TREATMENT DEVICE FOR PRODUCING BOTTLED WATER - A water treatment device for filling at least one bottle with treated tap water includes a housing unit having a reservoir, and at least one valve arranged in fluid communication with the reservoir, the valve having a water inlet/air exit port arranged adjacent to the housing unit, and a water exit/air inlet port arranged opposite the water inlet/air exit port, whereby when the valve is actuated to its open condition, water flows through the valve and into the bottle, and air entrapped in the bottle flows through the valve and into the surrounding environment. When the valve is in its closed condition, air and water do not flow through the valve. | 04-07-2011 |
20110079551 | WATER TREATMENT CARTRIDGE - A water treatment cartridge, or insert, for use in connection with a water treatment device such as a gravity-fed water pitcher or the like includes a support structure and water treatment material arranged in combination with the support structure. The support structure may, for example, generally enclose the water treatment material, or the support structure may be integrated into the structure of the water treatment material | 04-07-2011 |
20110079572 | BOTTLE FOR WATER TREATMENT DEVICE - A water bottle for use in connection with a water treatment device includes an opening with a diameter of at least about 0.87 inches, a diameter of no greater than about 1.06 inches, and a height of at least about 6.56 inches, and a height of no greater than about 8.02. | 04-07-2011 |