Lu, Hsin-Chu City
Chen-Hsiang Lu, Hsin-Chu City TW
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20150140692 | ADVANCED PROCESS CONTROL METHOD FOR CONTROLLING WIDTH OF SPACER AND DUMMY SIDEWALL IN SEMICONDUCTOR DEVICE - An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer. | 05-21-2015 |
Chung-Yu Lu, Hsin-Chu City TW
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20140167269 | Methods and Apparatus of Packaging with Interposers - Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost. | 06-19-2014 |
20140203397 | Methods and Apparatus for Inductors and Transformers in Packages - Methods and apparatus for forming a semiconductor device package with inductors and transformers using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top die and a bottom die, or between a die and an interposer. An inductor can be formed by a redistribution layer within a bottom device and a micro-bump line above the bottom device connected to the RDL. The inductor may be a symmetric inductor, a spiral inductor, a helical inductor which is a vertical structure, or a meander inductor. A pair of inductors with micro-bump lines can form a transformer. | 07-24-2014 |
David Lu, Hsin-Chu City TW
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20120038894 | Lens Cleaning Module - A lens cleaning module for a lithography system having an exposure apparatus including an objective lens is disclosed. The lens cleaning module includes a scanning stage for supporting a wafer beneath the objective lens. A cleaning module is provided adjacent to the scanning stage for cleaning the objective lens in a non-manual cleaning process. | 02-16-2012 |
David Ding-Chung Lu, Hsin-Chu City TW
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20080258303 | Novel structure for reducing low-k dielectric damage and improving copper EM performance - A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a dielectric layer; a chemical mechanical polish (CMP) stop layer on the dielectric layer; a conductive wiring in the dielectric layer; and a metal cap over the conductive wiring. | 10-23-2008 |
Fang-Chih Lu, Hsin-Chu City TW
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20080232099 | HOLDER STRUCTURE - The present invention discloses a holder structure for retaining at least one lamp and associated wire within a backlight module, which includes a main body, a reflector, and a first groove formed on an external sidewall of the main body. The main body has at least one first orienting slot for accommodating the lamp therein, and a second orienting slot for accommodating a high-voltage power wire therein. Said first groove communicates with the first and second orienting slots to divide a lateral slot wall of each of the first and second orienting slots into two opposite flexible walls which can provide flexibility required for assembly of the lamp and associated wire. Each two opposite flexible walls have two protrusions respectively formed on the outsides thereof for hooking with corresponding openings defined on the reflector, whereby the lamp and power wires are able to be firmly retained in the associated slots, respectively. | 09-25-2008 |
Jhi-Cherng Lu, Hsin-Chu City TW
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20120012047 | METHOD OF TEMPERATURE DETERMINATION FOR DEPOSITION REACTORS - A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer. | 01-19-2012 |
Shi-Hsiang Lu, Hsin-Chu City TW
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20080252362 | NEGATIVE VOLTAGE CONVERTER - A negative voltage converter includes six transistors. A first end and a control end of a first transistor are coupled to a signal input. A first end of a second transistor is coupled to the signal input, and a control end of which is coupled to a first clock and the first transistor. A first end of a third transistor is coupled to the signal input, a control end of the third transistor is coupled with a second clock and the second transistor. A first end of a fourth transistor is coupled to the second end of the third transistor, a control end of which is coupled with the first clock and the third transistor. A first end of a fifth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the second clock and the fourth transistor A first end of a sixth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the first clock and the fifth transistor. | 10-16-2008 |
Szu Wei Lu, Hsin-Chu City TW
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20140210074 | Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages - Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer. | 07-31-2014 |