Patent application number | Description | Published |
20090035903 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines. | 02-05-2009 |
20090207648 | MULTI-LEVEL DYNAMIC MEMORY DEVICE - A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal. | 08-20-2009 |
20090239345 | Methods of Fabricating Nonvolatile Semiconductor Memory Devices - A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines. | 09-24-2009 |
20110042746 | SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME - A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode. | 02-24-2011 |
20110069569 | SEMICONDUCTOR MEMORY DEVICE COMPRISING TRANSISTOR HAVING VERTICAL CHANNEL STRUCTURE - A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line. | 03-24-2011 |
20110163371 | METHODS OF FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICES - A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines. | 07-07-2011 |
20130051138 | PHASE CHANGE MEMORY - A phase change memory device including a voltage generator that generates an operating voltage by generating at least one modified clock signal, a pulse width of which is maintained constant for at least one clock cycle in response to a pump enable signal being enabled, from at least one reference clock signal, and performing a pump operation on a power supply voltage according to the at least one modified clock signal; and a memory cell array that includes a plurality of phase change memory cells connected between word lines and bit lines. The operating voltage is applied to the memory cell array so as to perform a data access operation. | 02-28-2013 |
20130336058 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches. | 12-19-2013 |
20140047168 | DATA STORAGE SYSTEM AND METHOD OF OPERATING DATA STORAGE SYSTEM - A method of operating a data storage device includes providing a memory cell array that includes a first word line, a second word line and a buffer configured to store second data to be programmed into the second word line, reading the second data from the buffer, and programming first data into the first word line. A programming condition of the first data being is changed based on the second data read from the buffer. | 02-13-2014 |