Patent application number | Description | Published |
20090116324 | Apparatus for Guaranteed Write Through in Domino Read SRAM'S - In a digital device for facilitating recovery of a precharged dot line, periodically precharged by a precharge signal, that has been prematurely discharged as a result of an early read condition, a data input signal can have a selected one of a first value and a second value. The first value is a value that would be reflected by the dot line being in a charged state. A logic device that is responsive to the data input signal causes charge to be applied to the dot line when the data signal has the first value. | 05-07-2009 |
20090175107 | Apparatus for and Method of Current Leakage Reduction in Static Random Access Memory Arrays - A novel and useful mechanism for reducing current leakage in a static random access memory array which significantly reduces the power requirements of the memory array. The method enables the steady state of all local and global bit lines in an SRAM array to be discharged during both active and inactive modes. The memory array consists of memory cells having an N channel field effect transistor read stack. A mechanism is provided to evaluate data from memory cells where the steady state of local and global read bit lines is discharged. | 07-09-2009 |
20090271669 | High-Speed Testing of Integrated Devices - A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device. | 10-29-2009 |
20090309644 | METHOD AND APPARATUS TO LIMIT CIRCUIT DELAY DEPENDENCE ON VOLTAGE - The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e.g. 0) or high voltage (e.g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant. | 12-17-2009 |
20100002495 | Column Selectable Self-Biasing Virtual Voltages for SRAM Write Assist - A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit further includes a write assist circuit having a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line. In response to a write assist signal, the write assist circuit connects one of the first and second cell supply lines selected by control circuitry to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the threshold transistor. | 01-07-2010 |
20100025479 | Doped Implant Monitoring for Microchip Tamper Detection - A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation. | 02-04-2010 |
20110109366 | Method and Apparatus to Limit Circuit Delay Dependence on Voltage for Single Phase Transition - A delay circuit receives a data input having an input transition and that generates a data output having an output transition. The delay circuit is powered by a voltage source having a voltage. A first delay element is configured to generate a first data signal with a first edge that has a relatively constant delay relative to the input transition irrespective of the voltage of the voltage source. A second delay element is configured to generate a second data signal with a second edge that has a delay relative to the input transition as a function of the voltage of the voltage source. A selection element causes the output transition at the data output to correspond to a latest selected one of the first edge and the second edge. The delay circuit may be employed in a pulse generating circuit. | 05-12-2011 |
20110304350 | Mask Alignment, Rotation and Bias Monitor Utilizing Threshold Voltage Dependence - The present invention provides a method and apparatus for measuring alignment, rotation and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation. | 12-15-2011 |
20120069688 | IMPLEMENTING SINGLE BIT REDUNDANCY FOR DYNAMIC SRAM CIRCUIT WITH ANY BIT DECODE - A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input. | 03-22-2012 |
20120147661 | DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY AT POWER-UP - A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. In a preferred embodiment, the wordlines are all turned on simultaneously during a power on reset period. Preferably a power on reset signal is used to drive each logic gate of the pre-decoder portion of the address decoder in order to assert all the wordlines. | 06-14-2012 |
20120195107 | Method for Selectable Guaranteed Write-Through With Early Read Suppression - A static random access memory with write-through capability includes a memory cell configured to store a bit of data. A write enable signal is configured to enable writing a write value from a write line input into the static random access memory cell and to enable reading a read value from the memory cell onto a DOT line. A local evaluation circuit is configured to place the write value from the write line onto the DOT line during a single clock cycle in which the value is being written into the memory cell. An early read suppression circuit is configured to electrically isolate the DOT line from a data out line thereby preventing a leakage current loss from the local evaluation circuit and is also configured to make the value placed on the DOT line to be read from the data out line during the single clock cycle. | 08-02-2012 |
20120281457 | Data Dependent SRAM Write Assist - A semiconductor chip has an SRAM (static random access memory). The SRAM includes a data dependent write assist circuit which, on writes, reduces a supply voltage on one of a cross coupled inverter pair in an SRAM cell, thereby making it easier to overcome the one of the cross coupled inverters. | 11-08-2012 |
20130020712 | IMPLEMENTING INTEGRATED CIRCUIT MIXED DOUBLE DENSITY AND HIGH PERFORMANCE WIRE STRUCTURE - A method and structures are provided for implementing an integrated circuit with an enhanced wiring structure of mixed double density and high performance wires in a common plane. A wiring structure includes a first wire having a first plane and a first via to a second wire in a second plane having a second via and a third wire having the first plane with height equal to the first wire and the first via, and a third via having a height equal to the second wire and the second via. | 01-24-2013 |
20130148454 | DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP - A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. | 06-13-2013 |
20130175631 | LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY - A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell. | 07-11-2013 |
20130222031 | IMPLEMENTING POWER SAVING SELF POWERING DOWN LATCH STRUCTURE - A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal. | 08-29-2013 |
20130235681 | IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM - A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal. | 09-12-2013 |
20130258758 | Single Cycle Data Copy for Two-Port SRAM - A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM. | 10-03-2013 |
20140092672 | POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation. | 04-03-2014 |
20140092696 | POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation. | 04-03-2014 |
20140124943 | INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA - A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region. | 05-08-2014 |
20140126273 | POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a precharge device connected between a voltage supply and the local bit line, and global bit line (GBL) discharge logic connected between a local bit line and a GBL. The GBL discharge logic transfers a logic value of the local bit line to the GBL during a read operation. GBL precharge logic connects the GBL to a global precharge input. The GBL precharge logic is adapted to draw the GBL to a precharge voltage above a discharge voltage and below a supply voltage during a precharge operation. | 05-08-2014 |
20140126276 | POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a precharge device connected between a voltage supply and the local bit line, and global bit line (GBL) discharge logic connected between a local bit line and a GBL. The GBL discharge logic transfers a logic value of the local bit line to the GBL during a read operation. GBL precharge logic connects the GBL to a global precharge input. The GBL precharge logic is adapted to draw the GBL to a precharge voltage above a discharge voltage and below a supply voltage during a precharge operation. | 05-08-2014 |
20140127875 | INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA - A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region. | 05-08-2014 |
20140149817 | DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY - A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space. | 05-29-2014 |
20140149818 | DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY - A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space. | 05-29-2014 |
20140169076 | POWER MANAGEMENT SRAM WRITE BIT LINE DRIVE CIRCUIT - A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage. | 06-19-2014 |
20140293679 | MANAGEMENT OF SRAM INITIALIZATION - An embodiment of the current disclosure is directed to a Static Random Access Memory (SRAM) device, and a design structure for the SRAM device. The SRAM device may include one or more SRAM cells. Each SRAM cell may further include a first and a second CMOS inverter that are cross-coupled. The first and second CMOS inverters may each have a first switch and a second switch. The SRAM device may also include a reset circuit. The reset circuit may be coupled to a first node of the first switch of the first CMOS inverter. The reset circuit may drive the first CMOS inverter to output a logical high signal in a reset mode. | 10-02-2014 |
20140353764 | LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY - A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell. | 12-04-2014 |
20150179261 | PARTIAL UPDATE IN A TERNARY CONTENT ADDRESSABLE MEMORY - A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry wi thout influence of the valid row cell. | 06-25-2015 |
20150179262 | PARTIAL UPDATE IN A TERNARY CONTENT ADDRESSABLE MEMORY - A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry without influence of the valid row cell. | 06-25-2015 |
20150349778 | LEVEL SHIFTER FOR A TIME-VARYING INPUT - A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit. | 12-03-2015 |
20150349779 | LEVEL SHIFTER FOR A TIME-VARYING INPUT - A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit. | 12-03-2015 |
Patent application number | Description | Published |
20090097029 | OPTICAL PRODUCT DETECTION SENSOR - An optical detection sensor detects presence or absence of a product within a fluid delivery medium. An emitter directs radiation into the fluid delivery medium. Each of a plurality of detectors detects light within an associated one of a plurality of wavelength ranges transmitted through the fluid delivery medium. The output of each detector is further associated with at least one out-of-product threshold. A controller may further combine detector outputs, such as by multiplication, summation, or other mathematical operation, to produce additional measures of product presence or absence. Each combination output is also associated with at least one out-of-product threshold. The controller compares the output of each detector with the associated out-of-product threshold(s) and compares each combination output with the associated out-of-product threshold(s) to determine presence or absence of product within the fluid delivery medium. The sensor is able to determine presence or absence of a variety of products having different color, transparency or turbidity. | 04-16-2009 |
20090098022 | MULTI-CHANNEL DEVICE AND METHOD FOR MEASURING OPTICAL PROPERTIES OF A LIQUID - A multi-channel device includes up to three channels for optical testing of liquid samples. The liquid sample(s) may include surface water, drinking water, processed water or the like. The multi-channel device may include a turbidity channel and a color channel that measure turbidity and color, respectively, of a liquid sample using spectrographic analysis. The multi-channel device may also include a colorimetric channel that measures the concentration of various analytes in a liquid sample, such as free chlorine, total chlorine, copper and phosphate. | 04-16-2009 |
20100103629 | DETACHABLE MODULE SYSTEM - A detachable module system includes a plurality of modules that couple to a corresponding plurality of module mounts on a mounting plate. To install a selected module into the module system, a user translates the selected module to an engage position on its respective module mount to engage the selected module with a immediately preceding adjacent module. Any one of the modules may be identified and removed from its module mount, without requiring removal of the remaining modules. The modules may house various types of electronic devices. | 04-29-2010 |
20110079491 | CONVEYOR CHAIN TENSION MONITOR - At least one single link of a conveyor chain is configured to support a tension load cell. A main body portion of the link includes a central cavity sized to contain the load cell, which has been inserted therein through an opening of the main body portion, and at least one auxiliary cavity to contain at least one battery cell and circuitry. A cap portion of the link closes off the opening into the cavity to enclose the load cell therein. One or both of the main body and cap portions may include a bore to receive a fastener for attaching to an end of the inserted load cell, and both portions include a bore oriented to receive a pin of a mating dual link of the conveyor chain. The cap portion may also include anti-rotation surfaces to mate with one or both of: the load cell and the opening. | 04-07-2011 |
20110240886 | Fluorometric Sensor - Embodiments provide an optical sensor head and method of making an optical sensor head. In some cases the sensor head can be used as a fluorometric sensor to measure concentrations of substances within a liquid sample of interest. The sensor head includes a light source window and a detector window that transmit light between the sensor head and an analytical area. In some cases the windows include a ball lens positioned within a channel such that the ball lens and the channel create a seal between the interior and exterior of the sensor head. | 10-06-2011 |
20110240887 | Handheld Fluorometer and Method of Use - Embodiments provide a handheld fluorometer and method of determining a concentration of a product within a sample. In some cases the handheld fluorometer includes an immersible sensor head that measures a fluorescence of the product and a controller that calculates the concentration of product. In some cases the handheld fluorometer includes a handheld controller module, an immersible sensor head connected to the controller module, a sample cup for containing a water sample, and a fastener that removably fastens the sample cup about the immersible sensor head. In some cases the sensor head is angled with respect to the controller module and the fluorometer provides a substantially stable base. The sample cup can be removed to acquire a sample of water containing the product and then refastened about the sensor head for determining the concentration. | 10-06-2011 |
20110242539 | Handheld Optical Measuring Device and Method of Use - Embodiments provide a handheld optical measuring device and method of measuring an optical property of a liquid sample. In some embodiments the optical measuring device includes a handheld controller module having an immersible sensor head and a sampling member including a sample cup and an attachment member that couples the sample cup to the handheld controller module. In some embodiments the attachment member is an elongated rigid member that is hingedly coupled to the controller module, thus providing a folding configuration for enclosing the sensor head with the sample cup during measurements, transportation, and/or storage. In some embodiments the attached sample cup provides a protective shell for the immersible sensor head during use and/or when not in use. | 10-06-2011 |
20120024080 | APPARATUS, METHOD AND SYSTEM FOR CALIBRATING A LIQUID DISPENSING SYSTEM - An apparatus, method and system providing for calibration and/or control of a liquid dispensing system is disclosed. The hand-held calibration auditing tool includes a flow meter ( | 02-02-2012 |
20120028364 | Stop-Flow Analytical Systems and Methods - Analytical systems and methods are provided for simultaneously dispensing metered volumes of fluids at different rates and mixing the fluids to generate a mixed sample having the fluids in proportion to the different rates at which they were dispensed. In some cases two or more of the fluids are premixed prior to mixing with other fluids. In some cases a use composition and diluent are simultaneously dispensed at different rates and premixed to form a diluted sample. One or more reagents may be mixed with the diluted sample and the sample mixture can be analyzed to determine characteristics of the use composition. | 02-02-2012 |
20120031195 | Fluid Flow Meter - Fluid flow meters and methods for measuring different aspects of fluid flow with a non-contact sensor are provided. In some cases a fluid flow gear meter is provided with a fluid chamber that is sealed with a cover portion carrying the non-contact sensor. An optional separation member may be located between the cover portion and the chamber to seal the chamber. In some cases the cover portion and/or separation member are configured to transmit visible light to allow viewing of the fluid chamber, through material selection and/or the presence of viewing cavities within the material. The flow meter is optionally configured to prevent or reduce the transmission of ambient environmental radiation into the flow meter to lessen the likelihood that it may adversely affect an optical non-contact sensor used to detect movement of gears within the chamber. | 02-09-2012 |
20130256557 | FLOW CHAMBER FOR ONLINE FLUOROMETER - A fluorescence analysis system may include a sensor head that has a light source configured to emit light into a flow of fluid, a detector configured to detect fluorescent emissions from the flow of fluid, and a temperature sensor. The system may also include a flow chamber that includes a housing defining a cavity into which the sensor head can be inserted. In some examples, the housing is configured such that, when a flow of fluid enters the housing, the flow of fluid divides into at least a major stream passing adjacent the light source and the detector and a minor stream passing adjacent the temperature sensor. Such a flow chamber may direct fluid past different sensors components while inhibiting a build-up of solids particles, the generation of air locks, or other flow issues attendant with continuous or semi-continuous online operation. | 10-03-2013 |
20130293881 | SELF-CLEANING OPTICAL SENSOR - An optical sensor may include a sensor head that has an optical window for directing light into a flow of fluid and/or receiving optical energy from the fluid. The optical sensor may also include a flow chamber that includes a housing defining a cavity into which the sensor head can be inserted. In some examples, the flow chamber includes an inlet port defining a flow nozzle that is configured to direct fluid entering the flow chamber against the optical window of the sensor head. In operation, the force of the incoming fluid impacting the optical window may prevent fouling materials from accumulating on the optical window. | 11-07-2013 |
20140034668 | APPARATUS, METHOD AND SYSTEM FOR CALIBRATING A LIQUID DISPENSING SYSTEM - An apparatus, method and system providing for calibration and/or control of a liquid dispensing system is disclosed. The hand-held calibration auditing tool includes a flow meter ( | 02-06-2014 |
20140109644 | APPARATUS, METHOD AND SYSTEM FOR CALIBRATING A LIQUID DISPENSING SYSTEM - An apparatus, method and system providing for calibration and/or control of a liquid dispensing system is disclosed. The hand-held calibration auditing tool includes a flow meter ( | 04-24-2014 |
20140260672 | FLUID FLOW METER - Systems and methods for determining a flow rate or volume of fluid. The system includes a positive displacement meter including a plurality of non-contact sensors and gears configured to rotate in response to fluid flow through the meter. The gears may include detectable areas that may be sensed by the plurality of non-contact sensors to determine a rotational direction of the gears. The plurality of non-contact sensors may also be configured to generate respective detection signals indicative of a rotation state of the gears. The controller may be configured to receive the detection signals, determine a current rotation state, and increment a rotational count based on the changes in the current rotation state. The controller may use the rotational count to determine a flow rate or volume of fluid. | 09-18-2014 |
20150177124 | SELF-CLEANING OPTICAL SENSOR - An optical sensor may include a sensor head that has an optical window for directing light into a flow of fluid and/or receiving optical energy from the fluid. The optical sensor may also include a flow chamber that includes a housing defining a cavity into which the sensor head can be inserted. In some examples, the flow chamber includes an inlet port defining a flow nozzle that is configured to direct fluid entering the flow chamber against the optical window of the sensor head. In operation, the force of the incoming fluid impacting the optical window may prevent fouling materials from accumulating on the optical window. | 06-25-2015 |
20150362086 | CHECK VALVE FOR A FLUID FLOW REGULATION SYSTEM - Embodiments include a flow regulating device. The flow regulating device may include a check valve. The check valve can have a first flange, a second flange and a ball seated against a seat defined by the first flange. The check valve is in a closed position when the ball is seated against the first flange. One or more stoppers may be positioned at a distance from the first flange. A fluid may flow through a first orifice and a second orifice defined in the first and second flanges respectively, when the first check valve is in an open position. The fluid lifts the ball from the first orifice, and pushes the ball towards the second orifice. The stoppers abut the ball when the first check valve is in a fully open position. | 12-17-2015 |
20160033407 | FLUOROMETER WITH MULTIPLE DETECTION CHANNELS - An optical sensor may have multiple detection channels to detect different characteristics of a fluid. For example, an optical sensor used in industrial cleaning and sanitizing applications may have multiple detection channels to detect when a system is both clean and properly sanitized. In one example, an optical sensor includes an optical emitter that directs light into a fluid, a first optical detector that detects light transmitted through the fluid, a second optical detector that detects light scattered by the fluid, and a third optical detector that detects fluorescent emissions emitted by the fluid. The optical emitter and optical detectors can be positioned around an optical analysis area. The optical sensor may include filters that control the characteristics of light detected by each of the optical detectors. | 02-04-2016 |