Patent application number | Description | Published |
20090278204 | SEMICONDUCTOR DEVICE - There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer. | 11-12-2009 |
20110024847 | SEMICONDUCTOR DEVICE - There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer. | 02-03-2011 |
20110266631 | SEMICONDUCTOR DEVICE - There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer. | 11-03-2011 |
Patent application number | Description | Published |
20100131898 | HISTORY DISPLAY APPARATUS, HISTORY DISPLAY SYSTEM, HISTORY DISPLAY METHOD, AND PROGRAM - According to an operation of a frame on an arrangement of history information displayed in a sequence, shared history information including action information which relates to action information having a first identifier selected by the frame and has a second identifier is obtained from a server. Identifiers included in action information items included in the shared history information are displayed in the sequence, in parallel with the arrangement of the history information so that the second identifier is displayed adjacent to the first identifier. Via the first and the second identifiers, the frame is moved between the arrangements of the history information and the shared history information, and according to an operation of the frame in the before-after direction of the sequence on the arrangement to which the frame is moved, an identifier included in an action information item in the before-after direction of the sequence is displayed. | 05-27-2010 |
20110283228 | INFORMATION PROCESSING APPARATUS AND METHOD, AND PROGRAM - An information processing apparatus includes a displaying section that displays a page including a plurality of text elements, a detecting section that detects a position designated by the user to be magnified, on the page displayed by the displaying section, a selecting section that selects one of the text elements which is located near the position detected by the detecting section, a placing section that places a character string of the text element selected by the selecting section, in a pop-up window so that the character string is displayed in the pop-up window, and a display controlling section that controls display so that the pop-up window in which the character string has been placed by the placing section is displayed on the page. | 11-17-2011 |
Patent application number | Description | Published |
20080273569 | SURFACE-EMITTING LASER DEVICE - A VCSEL device includes a polyimide having a larger thickness (d | 11-06-2008 |
20100232465 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A semiconductor light emitting element, comprises: an active layer; a first electrode and second electrode that inject current to the active layer; a semiconductor layer between the active layer and the first electrode; and a dielectric layer that is provided on the semiconductor layer and through which light from the active layer passes; wherein the first electrode is provided on the semiconductor layer, has an opening through which light from the active layer passes, and comprises a first electrode layer that comes in contact with and is provided on the semiconductor layer, and a second electrode layer that is provided on the first electrode layer, with the first electrode layer having less reactivity with the semiconductor layer than the second electrode layer; and the dielectric layer is provided inside the opening such that the end section on the opening side of the first electrode layer extends from the top of the semiconductor layer to the top of the dielectric layer. | 09-16-2010 |
20110003403 | TESTING METHOD OF SURFACE-EMITTING LASER DEVICE AND TESTING DEVICE THEREOF - A method of performing a wafer level burn-in test for a plurality of surface-emitting laser devices formed on a wafer includes causing a plurality of contact electrodes arranged in a same plane with a pitch same as that of the surface-emitting laser devices being electrically connected to each other to have contact with pad electrodes of the surface-emitting laser devices, respectively, and applying a current to second electrodes of the surface-emitting laser devices and the contact electrodes. The wafer level burn-in test is performed while heating the wafer at a predetermined temperature. Laser lights emitted from the surface-emitting laser devices are monitored during the wafer level burn-in test. | 01-06-2011 |
20110064108 | METHOD OF MANUFACTURING VERTICAL-CAVITY SURFACE EMITTING LASER AND VERTICAL-CAVITY SURFACE EMITTING LASER ARRAY - A method of manufacturing a surface emitting laser element of a vertical cavity type in accordance with the present invention is characterized in that comprises the following steps of: applying a process of accumulations on a substrate, the process sequentially including accumulating a reflecting mirror of a multilayered film layer at a lower side thereof on to the substrate, and accumulating layers of a semiconductor as a plurality thereof on to the reflecting mirror of the multilayered film layer at the lower side thereof, that comprises an active layer and that further comprises a contact layer at a top layer thereof as well; forming a first layer of a dielectric substance as a process of a formation of the first layer of the dielectric substance at a part of regions on the contact layer; forming an electrode of an annular shape as a process of a formation of the electrode of the annular shape on the contact layer, that has an open part at a center thereof, in order to be arranged for the first layer of the dielectric substance at an inner side of the open part thereat; forming a second layer of a dielectric substance as a process of a formation of the second layer of the dielectric substance in order to cover the first layer of the dielectric substance and to cover a gap which is formed between the first layer of the dielectric substance and the electrode of the annular shape; and etching the layers of the semiconductor as a process of a formation of a mesa post that are accumulated thereon, thereby etching to be a shape of the mesa post with making use of the electrode of the annular shape to be as a mask therefor. | 03-17-2011 |
20110076854 | METHOD OF MANUFACTURING VERTICAL-CAVITY SURFACE EMITTING LASER - According to a method of manufacturing a vertical-cavity surface-emitting semiconductor laser element in accordance with the present invention, a process of wet etching is performed for a part that is oxidized in a layer of an AlGaAs ( | 03-31-2011 |