Patent application number | Description | Published |
20090204460 | Method and System For Workforce Optimization - A method, system and computer program product for workforce optimization in a service oriented industry, the method comprising planning and executing a business scheme which include providing as input business planning parameters relevant to the business scheme; developing a business plan to execute the business scheme based on the business planning parameters; identifying and allocating relevant resources for executing the business plan; intimating the identified resources with the plan to execute the business scheme. | 08-13-2009 |
20090204461 | METHOD AND SYSTEM FOR WORKFORCE OPTIMIZATION - A system for workforce optimization in a service oriented industry, the system comprising a workforce optimization unit configured for planning and executing a business scheme which include providing as input business planning parameters relevant to the business scheme; developing a business plan to execute the business scheme based on the business planning parameters; identifying and allocating relevant resources for executing the business plan; intimating the identified resources with the plan to execute the business scheme. | 08-13-2009 |
20100036690 | SERVICE SCHEDULING - Techniques for scheduling one or more services are provided. The techniques include obtaining customer information, obtaining one or more service characteristics for each of the one or more services, and using the customer information and the one or more service characteristics to schedule the one or more services. | 02-11-2010 |
20100198735 | AUTOMATED ITEM PRICING - Techniques for automated pricing of an item are provided. The techniques include obtaining historical data of one or more previous purchases for the item, performing a regression on the historical data, and using the regression to obtain a buying price and a selling price for the item. | 08-05-2010 |
Patent application number | Description | Published |
20110131379 | PROCESSOR AND METHOD FOR WRITEBACK BUFFER REUSE - A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writeback data has been evicted from the writeback cache and before the writeback data has been sent to the lower-level memory. After the writeback data has been sent from the writeback buffer to the lower-level memory, and before the lower-level memory has acknowledged completion of the first writeback operation, the writeback cache may perform a second writeback operation to store different writeback data in the writeback buffer in response to eviction of the different writeback data, such that a total size of the writeback data for the concurrently outstanding writeback operations exceeds a total size of writeback data that the writeback buffer is capable of concurrently storing. | 06-02-2011 |
20110153942 | REDUCING IMPLEMENTATION COSTS OF COMMUNICATING CACHE INVALIDATION INFORMATION IN A MULTICORE PROCESSOR - A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores. | 06-23-2011 |
20110185125 | RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR - A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently. | 07-28-2011 |
20120239883 | RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR - A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure. | 09-20-2012 |
20150019824 | CACHE PRE-FETCH MERGE IN PENDING REQUEST BUFFER - An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a pending request buffer and a control circuit. The pending request buffer may include a plurality of buffer entries. The control circuit may be coupled to the pending request buffer and may be configured to receive a request for a first cache line from a pre-fetch engine, and store the received request in an entry of the pending request buffer. The control circuit may be further configured to receive a request for a second cache line from a processor, and store the request received from the processor in the entry of the pending request buffer in response to a determination that the second cache line is the same as the first cache line. | 01-15-2015 |
20150026404 | Least Recently Used Mechanism for Cache Line Eviction from a Cache Memory - A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory. | 01-22-2015 |