Troccoli
Alejandro Troccoli, San Jose, CA US
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20130329015 | TECHNIQUES FOR GENERATING ROBUST STEREO IMAGES - Techniques for generating robust depth maps from stereo images are described. A robust depth map is generated from a set of stereo images captured with and without flash illumination. The depth map is more robust than depth maps generated using conventional techniques because a pixel-matching algorithm is implemented that weights pixels in a matching window according to the ratio of light intensity captured using different flash illumination levels. The ratio map provides a rough estimate of depth relative to neighboring pixels that enables the flash/no-flash pixel-matching algorithm to devalue pixels that appear to be located at different depths than the central pixel in the matching window. In addition, the ratio map may be used to filter the generated depth map to generate a smooth estimate for the depth of objects within the stereo image. | 12-12-2013 |
Alejandro Troccoli, Santa Clara, CA US
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20110063304 | CO-PROCESSING SYNCHRONIZING TECHNIQUES ON HETEROGENEOUS GRAPHICS PROCESSING UNITS - The graphics co-processing technique includes receiving display operation for execution by a graphics processing unit on an unattached adapter. The display operation is split into a copy from a frame buffer of the graphics processing unit on the unattached adapter to a buffer in system memory, a copy from the buffer in system memory to a frame buffer of graphics processing unit on a primary adapter, and a present from the frame buffer of the graphics processing unit on the primary adapter to a display. Execution of the copy from the frame buffer of the graphics processing unit on the unattached adapter to the buffer in system memory and the copy from the buffer in system memory to the frame buffer of the graphics processing unit on the primary adapter are synchronized. | 03-17-2011 |
20110063305 | CO-PROCESSING TECHNIQUES ON HETEROGENEOUS GRAPHICS PROCESSING UNITS - The graphics co-processing technique includes loading and initializing a device driver interface and a device specific kernel mode driver for a graphics processing unit on a primary adapter. A device driver interface and a device specific kernel mode driver for a graphics processing unit on an unattached adapter is also loaded and initialized without the device driver interface talking back to a runtime application programming interface or a thunk layer when a particular versions of an operating system will not allow the device driver interface on the unattached adapter to be loaded. | 03-17-2011 |
20110067038 | CO-PROCESSING TECHNIQUES ON HETEROGENEOUS GPUS HAVING DIFFERENT DEVICE DRIVER INTERFACES - The graphics co-processing technique includes loading a shim layer library. The shim layer library loads and initializes a device driver interface of a first class on the primary adapter and a device driver interface of a second class on an unattached adapter. The shim layer also translates calls between the first device driver interface of the first class on the primary adapter and the second device driver interface of the second class on the unattached adapter. | 03-17-2011 |
Edson Troccoli, Santana De Parnaiba - Sp BR
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20120210889 | ARRANGEMENT INSERTED INTO A COMPACTING ASSEMBLY USED IN A MANUAL GARLIC PRESS - An arrangement inserted into a compacting device applied in a manual garlic masher is disclosed, more specifically, a garlic masher equipped with a compacting device that allows for total pressure to be applied to garlic bulbs contained inside a receptacle ( | 08-23-2012 |
Joseph E. Troccoli, Madison, TN US
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20080232977 | Pump Control - A pump control system for controlling a fluid pump powered by an AC signal. The pump control system includes a signal phase detector coupled to the fluid pump to detect the AC signal supplied to the fluid pump and to generate phase signals indicating a phase parameter of the AC signal. The pump control system also includes a micro-controller to receive the phase signals and to generate a rectified output signal based on the phase signals, and a relay to control the power supplied to the fluid pump based on the output signal of the micro-controller. | 09-25-2008 |
Mariano Troccoli, Paris FR
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20080259983 | SEMICONDUCTOR QUANTUM CASCADE LASER AND SYSTEMS AND METHODS FOR MANUFACTURING THE SAME - A bipolar quantum cascade (QC) laser includes a p-n junction disposed adjacent to an active/injection region of semiconductor layers. Systems that make use of such QC lasers and methods for manufacturing such QC lasers are also described. | 10-23-2008 |
Matias Troccoli, Kirkland, WA US
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20110267033 | LOW NOISE READING ARCHITECTURE FOR ACTIVE SENSOR ARRAYS - A sensor apparatus includes an array of active sensor elements arranged in columns and rows. Each sensor element is associated with a thin film access device disposed in a first current path through which an activation current is provided to activate the sensor element. Each sensor element is read through a respective second current path. The second current paths do not include the thin film access device of the first current path. As such, noise from the thin film access device is isolated from the second current paths. | 11-03-2011 |
Matias N. Troccoli, Kirkland, WA US
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20110211611 | VOLTAGE READING TECHNIQUE FOR LARGE SENSOR ARRAYS THROUGH REDUCED NOISE DIFFERENTIAL PATH - An active sensor apparatus includes an array of sensor elements arranged in a plurality of columns and rows of sensor elements. The sensor apparatus includes a plurality of column and row thin film transistor switches for selectively activating the sensor elements, and a plurality of column and row thin film diodes for selectively accessing the sensor elements to obtain information from the sensor elements. The thin film transistor switches and thin film diodes are formed on a common substrate. | 09-01-2011 |
20110221474 | NON-BINARY DECODER ARCHITECTURE AND CONTROL SIGNAL LOGIC FOR REDUCED CIRCUIT COMPLEXITY - A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log | 09-15-2011 |
20130300457 | NON-BINARY DECODER ARCHITECTURE AND CONTROL SIGNAL LOGIC FOR REDUCED CIRCUIT COMPLEXITY - A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log | 11-14-2013 |