Patent application number | Description | Published |
20080211023 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a first semiconductor layer and a second semiconductor layer facing each other across a back gate insulation film, a first conductive type plate provided in the first semiconductor layer, a gate insulation film provided on a surface of the second semiconductor layer so as to be in contact with a second surface opposite to a first surface in contact with the back gate insulation film, a gate electrode provided so as to be in contact with the gate insulation film, a first conductive type body region provided in the region facing the gate electrode across the gate insulation film in the second semiconductor layer, a second conductive type source layer and a second conductive type drain layer provided to sandwich the body region in the second semiconductor layer and a second conductive type diffusion layer provided in a surface region of the first semiconductor layer facing the source layer and the drain layer across the back gate insulation film, wherein the body region is in an electrically floating state and stores data by accumulating or discharging charges. | 09-04-2008 |
20080237695 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region. | 10-02-2008 |
20080239789 | SEMICONDUCTOR MEMORY DEVICE - The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film. | 10-02-2008 |
20080277725 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a memory comprising a semiconductor layer extending in a first direction; a source; a drain; a body between the source and the drain; a bit-line extending in the first direction; a first gate-dielectric on a first side-surface of the body; a first gate-electrode on the first side-surface of the body via the first gate dielectric film; a first gate line extending in the first direction, connected to a bottom of the first gate-electrode, and formed integratedly with the first gate-electrode using same material; a second gate dielectric on a second side-surface of the body; a second gate-electrode on the second side surface of the body via the second gate dielectric film; and a second gate line extending in a second direction crossing the first direction, connected to an upper portion of the second gate-electrode, and formed integratedly with the second gate-electrode using same material. | 11-13-2008 |
20090189222 | SEMICONDUCTOR MEMORY DEVICE - A memory includes a U-shape layer on a substrate; a first diffusion layer provided at an upper part of the U-shaped layer; a second diffusion layer provided at a lower part of the U-shaped layer; a body formed at an intermediate portion of the U-shaped layer between the first and the second diffusion layers; a first gate dielectric film provided on an outer side surface of the U-shaped layer; a first gate electrode provided on the first gate dielectric film; a second gate dielectric film provided on an inner side surface of the U-shaped layer; a second gate electrode provided on the second gate dielectric film; a bit line contact connecting the bit line to the first diffusion layer; a source line contact connecting the source line to the second diffusion layer, wherein cells adjacent in the first direction alternately share the bit line contact and the source line contact. | 07-30-2009 |
20090213675 | SEMICONDUCTOR MEMORY DEVICE - A memory includes memory cells, wherein in a first cycle of writing first logic data, sense amplifiers apply a first potential to bit lines, drivers apply a second potential to a selected word line and a third potential to a selected source line, and the second and third potentials with reference to the first potential have the same polarities as polarities of the carriers, and in a second cycle of writing second logic data, the sense amplifiers apply a fourth potential to a selected bit line, the drivers apply a fifth potential to the selected word line and a sixth potential to the selected source line and, the sixth potential is nearer to the first potential than the second and third potentials, the fifth potential with reference to the sixth potential has the same polarity as polarities of the carriers, and the fourth potential with reference to the sixth potential has a polarity opposite to the polarities of the carriers. | 08-27-2009 |
20100019304 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains. | 01-28-2010 |