Patent application number | Description | Published |
20110222633 | HIGH DYNAMIC RANGE RADIO ARCHITECTURE WITH ENHANCED IMAGE REJECTION - A circuit for down-converting an RF signal to a baseband signal includes a trans-admittance amplifier adapted to receive the RF signal and generate in response a pair of differential current signals. The circuit further includes a trans-impedance amplifier having at least four mixers and at least four linear amplifiers. The four mixers frequency down-convert the pair of differential current signals to generate four pairs of differential baseband current signals, wherein each pair of the differential baseband current signals has a different phase and is associated with each of the linear amplifiers. Additionally, the circuit includes a summing block that generates an in-phase signal using a first weighted sum of the four different baseband current signals and a quadrature signal using a second weighted sum of the four different baseband current signals. The circuit further includes an analog-to-digital converter for converting the in-phase and quadrature signals to respective digital representations. | 09-15-2011 |
20130203368 | Method and System for a Baseband Cross-Bar - Methods and systems for a baseband cross-bar may comprise receiving one or more radio frequency (RF) signals in a wireless communication device via antennas coupled to a plurality of receiver paths in the wireless device. The received RF signals may be converted to baseband frequencies. One or more of the down-converted signals may be coupled to receiver paths utilizing a baseband cross-bar. The baseband cross-bar may comprise a plurality of switches, which may comprise CMOS transistors. In-phase and quadrature signals may be processed in the one or more of the plurality of receiver paths. The one or more RF signals comprise cellular signals and/or global navigation satellite signals. A single-ended received RF signal may be converted to a differential signal in one or more of the plurality of receiver paths. The baseband cross-bar may be controlled utilizing a reduced instruction set computing (RISC) processor. | 08-08-2013 |
20130230078 | Configurable, Highly-Integrated Satellite Receiver - A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters. | 09-05-2013 |
20130268979 | Method And System For Full Spectrum Capture Sample Rate Adaptation - An electronic device may be operable to sample a signal during an analog-to-digital conversion using an analog-to-digital converter in the electronic device, and the signal may comprise a wide bandwidth and a plurality of channels. The electronic device may adaptively change a sample rate of the sampling to move aliasing out of a region of one or more desired channels of the plurality of channels. The electronic device may change the sample rate using a variable oscillator in the electronic device. The change of the sample rate may comprise, for example, increasing or decreasing the sample rate by a particular percentage. In response to the change of the sample rate, the electronic device may perform, using a variable rate interpolator in the electronic device, variable rate interpolation. The variable rate interpolator may comprise, for example, a finite impulse response filter. | 10-10-2013 |
20130337740 | Method And System For Guard Band Detection And Frequency Offset Detection - A signal processing circuit, which is within a satellite reception assembly, may be operable to analyze actual frequency information corresponding to a plurality of downconverted signals. Each of the downconverted signals may be downconverted using one or more corresponding local oscillators (LOs). Based on the analyzing, one or more of the following may be determined: one or more frequency offsets associated with the one or more corresponding LOs and one or more actual guard bands. The signal processing circuit may generate information on the determined frequency offsets and the determined actual guard bands. The signal processing circuit may perform, based on the generated information, one or both of a band stacking operation and a channel stacking operation so as to prevent channels/bands being stacked on each other or being overlapped. The signal processing circuit may perform, based on the generated information, frequency corrections for channel tuning in a gateway. | 12-19-2013 |
20140003559 | Method And System For Improved Cross Polarization Rejection And Tolerating Coupling Between Satellite Signals | 01-02-2014 |
20140015703 | METHOD AND SYSTEM FOR GAIN CONTROL FOR TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTOR (ADC) - A system for processing signals may be configured to apply digital conversion to analog signals, and to apply, prior to the analog-to-digital conversion, a gain to at least a portion of the analog signals. The gain may be controlled and/or adjusted based on processing of digital output generated based on the analog-to-digital conversion. The system may comprise a plurality of sampling slices, which may be configured to provide the analog-to-digital conversion in interleaved (e.g., time-interleaved) manner. Each of the sampling slices may comprise a dedicated gain element, for applying gain to signals handled by the corresponding slice. The gain applied by the gain elements of the sampling slices may be controlled, independently, collectively, and/or in based on grouping into subsets. The gain may be controlled based on application of a particular gain control algorithm, which may be selected from a plurality of predefined algorithms. | 01-16-2014 |
20140300499 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM - Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | 10-09-2014 |
20140329481 | BAND TRANSLATION WITH PROTECTION OF IN-HOME NETWORKS - Methods and systems are provided for band translation with protection. A signal processing circuitry (chip) may be configured to handle a plurality of signals, comprising at least a first signal corresponding to internal communication within an in-premises network and at least a second signal originating from a source external to the in-premises network; and to process on-chip the plurality of input signals, to generate one or more output signals. In this regard, at least one output signal may comprise components corresponding to the first signal and the second signal; and the processing may be configured to mitigate on-chip, during generating of the one or more outputs, at least one effect of including in the at least one output signal a first component corresponding to one of the first signal and the second signal on a second component corresponding to the other one of the first signal and the second signal. | 11-06-2014 |
20150063508 | HIGH DYNAMIC RANGE RADIO ARCHITECTURE WITH ENHANCED IMAGE REJECTION - A circuit for down-converting an RF signal to a baseband signal includes a trans-admittance amplifier adapted to receive the RF signal and generate in response a pair of differential current signals. The circuit further includes a trans-impedance amplifier having at least four mixers and at least four linear amplifiers. The four mixers frequency down-convert the pair of differential current signals to generate four pairs of differential baseband current signals, wherein each pair of the differential baseband current signals has a different phase and is associated with each of the linear amplifiers. Additionally, the circuit includes a summing block that generates an in-phase signal using a first weighted sum of the four different baseband current signals and a quadrature signal using a second weighted sum of the four different baseband current signals. The circuit further includes an analog-to-digital converter for converting the in-phase and quadrature signals to respective digital representations. | 03-05-2015 |
20150084795 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM - Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | 03-26-2015 |
20150085904 | Modular Microwave Backhaul Outdoor Unit - A microwave backhaul system may comprise a monolithic integrated circuit comprising an on-chip transceiver, digital baseband processing circuitry, and auxiliary interface circuitry. The on-chip transceiver may process a microwave signal from an antenna element to generate a first pair of quadrature baseband signals and convey the first pair of phase-quadrature baseband signals to the digital baseband processing circuitry. The auxiliary interface circuitry may receive one or more auxiliary signals from a source that is external to the monolithic integrated circuit and convey the one or more auxiliary signals to the digital baseband processing circuitry. The digital baseband processing circuitry may be operable to process signals to generate one or more second pairs of phase-quadrature digital baseband signals. | 03-26-2015 |
20150087226 | Microwave Backhaul System Supporting Multiple Installation Configurations - A monolithic integrated circuit for use in a microwave backhaul system may comprise a plurality of microwave transceivers and outdoor-unit to indoor-unit (ODU/IDU) interface circuitry. The monolithic integrated circuit may be configurable into an all-outdoor configuration in which the ODU/IDU interface circuitry is disabled. The monolithic integrated circuit may be configurable into a split-indoor-and-outdoor configuration in which the ODU/IDU interface circuitry is enabled to communicate signals between an outdoor unit of the microwave backhaul system and an indoor unit of the microwave backhaul system. While the monolithic integrated circuit is configured in the split-indoor-and-outdoor configuration, the ODU/IDU interface circuitry may be configurable to operate in at least a non-stacking mode and a stacking mode. | 03-26-2015 |
20150207461 | DYNAMIC BIASING OF POWER AMPLIFIERS - Systems and methods are provided for dynamically biasing power amplifiers. In particular, dynamic biasing of a power amplifier may be controlled, with the controlling comprising receiving an input signal that is to be amplified; processing the input signal; generating based on said processing of the input signal input signal, a plurality of control signals comprising at least one biasing control signal; and applying the plurality of control signals to one or more control elements that are used in driving and/or control of the power amplifier. The one or more control elements may comprise at least one biasing component that adjusts biasing applied to power amplifier. | 07-23-2015 |
20150256248 | Method And System For Guard Band Detection And Frequency Offset Detection - Methods and systems are provided for guard band detection and/or frequency offset detection. For example, a signal processing circuit may be operable to determine, for each of a plurality of downconverted signals, one or more frequency offsets that are associated with one or more corresponding local oscillators (LOs) used in obtaining the plurality of downconverted signals; and relating to the determined frequency offsets may be generated for the plurality of downconverted signals. The signal processing circuit may perform, based on the generated information, one or both of a band stacking operation and a channel stacking operation so as to prevent channels/bands being stacked on each other or being overlapped. | 09-10-2015 |
20150365100 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM - Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | 12-17-2015 |
Patent application number | Description | Published |
20120134401 | SYSTEM AND METHOD FOR CLOSED LOOP POWER CONTROL CALIBRATION - A system for calibrating a closed power control loop includes an adder configured to inject a test signal into an adjustable element, a first peak detector configured to determine an amplitude of the injected test signal, a second peak detector configured to determine an amplitude of a return test signal, a comparator configured to determine the difference between the injected test signal and the return test signal, and a calibration engine configured to adjust the adjustable element so that the return test signal is offset from the injected test signal by a predetermined amount. | 05-31-2012 |
20120170624 | SYSTEMS AND METHODS FOR POWER CONTROL IN A MULTIPLE STANDARD MOBILE TRANSMITTER - A transmitter adjusts a transmitted power level by modifying a control input of a variable gain amplifier. A power amplifier control system includes an envelope extractor, an error extractor, and a feed-forward multiplier. The envelope extractor receives data signal inputs and computes the envelope of the combined signal. The error extractor generates an error signal as a function of the combined signal and the output power generated by the power amplifier. The feed-forward multiplier generates a modified error signal that is responsive to a function of the gain in a feedback path. A corresponding method for controlling a power level is also disclosed. In some embodiments, a transmit chain with a power control loop is used to adjust the transmit signal power applied at an input of a variable gain amplifier. A corresponding method for adjusting the transmit signal power level is also included. | 07-05-2012 |
20120171973 | SYSTEMS AND METHODS FOR IMPLEMENTING A HARMONIC REJECTION MIXER - Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics. | 07-05-2012 |
20140198835 | METHOD AND SYSTEM FOR A MULTI-STANDARD RECEIVER - A multi-standard receiver may comprise in an electronic device, receiving an input radio frequency (RF) signal comprising at least two RF signals of different communication standards. The input RF signal may be separated into two signals based on their different communication standard sand configurable gain levels may be applied to equalize their magnitudes. The amplified signals may be combined, and the combined signals may be converted to a digital signal. The configurable gain may be applied to the two signals using variable gain amplifiers. A null may be generated at the input of at least one of the variable gain amplifiers utilizing a mixer and a filter, both configured to a desired frequency. The desired frequency may correspond to an interferer signal. The input RF signal may be separated into two signals utilizing a diplexer. The input RF signal may be received from a wired connection and/or an antenna. | 07-17-2014 |
20150023450 | APPARATUS AND METHODS FOR POWER CONTROL IN MOBILE COMMUNICATION DEVICES - Apparatus and methods for power control in mobile communication devices are provided. In one aspect, a method for accurately controlling an adjustable power level of a data signal in a transmit chain of a transmitter is provided. The method includes adjusting a controllable gain level of a digital-to-analog converter based on a desired peak-to-average ratio of a transmit signal envelope, adjusting a digitally controlled discrete gain-step amplifier, the amount of gain per step based on an initial estimate of the transmitter gain and a target power, applying a factor to a gain adjuster responsive to the gain step change in the transmit chain, and repeating the adjusting and applying steps until a feedback signal level exceeds a reference signal level. | 01-22-2015 |
20150333785 | SAW-LESS, LNA-LESS LOW NOISE RECEIVER - A low noise receiver includes a downconverter configured to receive a radio frequency (RF) signal, the downconverter comprising a switching architecture configured to generate a plurality of output phases based on a respective plurality of local oscillator (LO) signals, a differencing circuit configured to combine the plurality of output phases such that an nth output phase is differenced with an (n+K)th output phase, resulting in gain-added output phases, and a summation filter configured to receive the gain-added output phases and configured to combine the gain-added output phases such that a response of the receiver effectively reduces odd harmonics of the RF signal. | 11-19-2015 |