Patent application number | Description | Published |
20080201622 | Non-Volatile Memory Device Manufacturing Process Testing Systems and Methods Thereof - Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module. | 08-21-2008 |
20080209112 | High Endurance Non-Volatile Memory Devices - High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM. | 08-28-2008 |
20080209114 | Reliability High Endurance Non-Volatile Memory Device with Zone-Based Non-Volatile Memory File System - Improved reliability high endurance non-volatile memory device with zone-based non-volatile memory file system is described. According to one aspect of the present invention, a zone-based non-volatile memory file system comprises a two-level address mapping scheme: a first level address mapping scheme maps linear or logic address received from a host computer system to a virtual zone address; and a second level address mapping scheme maps the virtual zone address to a physical zone address of a non-volatile memory module. The virtual zone address represents a number of zones each including a plurality of data sectors. Zone is configured as a unit smaller than data blocks and larger than data pages. Each of the data sector consists of 512-byte of data. The ratio between zone and the sectors is predefined by physical characteristics of the non-volatile memory module. A tracking table is used for correlating the virtual zone address with the physical zone address. Data programming and erasing are performed in a zone basis. | 08-28-2008 |
20080215800 | Hybrid SSD Using A Combination of SLC and MLC Flash Memory Arrays - Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array. | 09-04-2008 |
20080215802 | High Integration of Intelligent Non-volatile Memory Device - High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically. | 09-04-2008 |
20080248692 | Extended Memory Card and Manufacturing Method - An embodiment of the present invention includes an extended memory card comprising memory circuitry, extended memory controller circuitry, a plurality of first format connection fingers, and a plurality of second format connection fingers. The memory circuitry is operable to store data files therein. The extended memory controller circuitry is operable to control data file storage and retrieval to and from the memory circuitry. | 10-09-2008 |
20080256287 | Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device - Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM. | 10-16-2008 |
20080256352 | Methods and systems of booting of an intelligent non-volatile memory microcontroller from various sources - Methods and systems of booting an intelligent non-volatile memory (NVM) microcontroller from various sources are described. According to one aspect of the present invention, a NVM microcontroller comprises multiple memory interfaces. Each of the memory interfaces may connect to one of the various sources for booting. The sources may include random access memory (RAM), read-only memory (ROM), Electrically Erasable Programmable ROM (EEPROM) (e.g., NOR flash memory, NAND flash memory). RAM may include static RAM (SRAM), dynamic RAM (DRAM), and synchronous dynamic RAM (SDRAM). Other sources include Secure Digital (SD) card and intelligent non-volatile memory devices. The NAND flash memory may include single-level cell (SLC) flash or multi-level cell (MLC) flash. SLC flash uses a single level per cell or two states per cell, while MLC flash stores four, eight or more states per cell. | 10-16-2008 |
20080261449 | UNIVERSAL SERIAL BUS (USB) FLASH DRIVE HOUSING A SLIM USB DEVICE AND HAVING SWIVEL CAP FUNCTIONALITIES ALLOWING FOR TWO LOCKING POSITIONS - A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end and a swivel cap having a side slit that serves as an opening into which the slim USB device travels horizontally, the side slit being disposed along a lateral side of the swivel cap. The USB flash drive also includes a USB device rivet placed into the slim USB device and the swivel cap to pivotally connect them at one of the ends of the slim USB device, so that the slim USB device is pivotally extendable outwardly from the side slit in a closed or open position. The swivel rocker is pivotally extendable outwardly from the opposite end of the slim USB device and when the swivel rocker is extended outwardly, the slim USB device is caused to extend outwardly | 10-23-2008 |
20080261450 | PORTABLE AND RETRACTABLE FLASH DRIVE WITH OPTIONAL ROTARY DEPLOYING AND RETRACTING AND FINGERPRINT VERIFICATION CAPABILITY - In one embodiment of the present invention a portable and retractable flash drive with optional rotary deploying and retracting and fingerprint verification capability is disclosed to include a cylinder assembly. The cylinder assembly has a connector situated on one end, and a fingerprint sensor situated the surface. The portable and retractable flash drive with optional rotary deploying and retracting and fingerprint verification capability further includes a rotary tube at least partially enclosing the cylinder assembly for deploying the connector. An end tube is rotatably attached to one of the two ends of the rotary tube, and an end cap is attached to the other of the two ends of the rotary tube. The rotary tube is rotated relative to the end tube to slide the cylinder assembly back and forth inside the rotary tube to extend and retract the connector. | 10-23-2008 |
20080278902 | Universal Serial Bus (USB) Flash Drive with Swivel Cap Functionalities with Two Locking Positions - A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end, and a swivel “strap shaped” metal cap having a circle cut out disposed on both cap legs. The snap coupling circle attachment allows the swivel cap to rotate substantially into a first and a second locking position and to rotate substantially 360 degrees about the z-axis of the USB device. The metal cap is generally in a locked position when the snap slot is aligned atop the snap lock tabs such that the protrusion snap ring is descended downward until the positioned flush against the snap lock groove. When unlocked the protrusion snap ring is raised up and rested upon the two snap lock tabs. | 11-13-2008 |
20080278903 | Package and Manufacturing Method for Multi-Level Cell Multi-Media Card - An embodiment of the present invention includes an electronic data flash memory card (memory card) comprising a top cover (TC), a printed circuit board assembly (PCBA) and a bottom cover (BC). The TC includes a plurality of ultrasonic bonders, a plurality of breakaway tabs (tabs) and a connection device. The PCBA includes at least one memory integrated circuit (IC) and at least one controller IC. The BC includes a plurality of tabs. | 11-13-2008 |
20080282128 | Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance - An electronic data storage device having a Reed Solomon (RS) decoder including a syndrome calculator block responsive to information including data and overhead and operative to generate a syndrome, in accordance with an embodiment of the present invention. The electronic data storage device further includes a root finder block coupled to receive said syndrome and operative to generate at least two roots, said RS decoder for processing said two roots to generate at least one error address identifying a location in said data wherein said error lies; and an erasure syndrome calculator block responsive to said information and operative to generate an erasure syndrome, said RS decoder responsive to said information identifying a disk crash, said RS decoder for processing said erasure syndrome to generate an erasure error to recover the data in said disk crash. | 11-13-2008 |
20080320209 | High Performance and Endurance Non-volatile Memory Based Storage Systems - High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge, while the page buffers are configured to hold data to be transmitted between the host computer and the at least one NVM device. | 12-25-2008 |
20110029723 | Non-Volatile Memory Based Computer Systems - Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives. | 02-03-2011 |
20110093653 | MEMORY ADDRESS MANAGEMENT SYSTEMS IN A LARGE CAPACITY MULTI-LEVEL CELL (MLC) BASED FLASH MEMORY DEVICE - Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM. | 04-21-2011 |
20110197017 | High Endurance Non-Volatile Memory Devices - High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM. | 08-11-2011 |