Patent application number | Description | Published |
20110049695 | Semiconductor Device and Method of Forming Pre-Molded Semiconductor Die Having Bumps Embedded in Encapsulant - A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected to contact pads on an active surface of the die. The bumps can also be pillars or stud bumps. A first encapsulant is deposited over the bumps. The semiconductor wafer is singulated to separate the die by cutting channels partially through the wafer and back grinding the wafer down to the channels. A second encapsulant is deposited over the die. A first interconnect structure is formed over a first surface of the second encapsulant. The first interconnect structure is electrically connected to the bumps. A second interconnect structure is formed over a second surface of the second encapsulant. Secondary semiconductor components can be stacked over the second interconnect structure. A third encapsulant is deposited over the stacked secondary components and second interconnect structure. | 03-03-2011 |
20110068444 | Semiconductor Device and Method of Forming Open Cavity in TSV Interposer to Contain Semiconductor Die in WLCSMP - A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer. | 03-24-2011 |
20110068459 | Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die - A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die. | 03-24-2011 |
20110186977 | Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die. | 08-04-2011 |
20110278707 | Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die - A prefabricated multi-die leadframe having a plurality of contact pads is mounted over a temporary carrier. A first semiconductor die is mounted over the carrier between the contact pads of the leadframe. A second semiconductor die is mounted over the contact pads of the leadframe and over the first die. An encapsulant is deposited over the leadframe and first and second die. The carrier is removed. A first interconnect structure is formed over the leadframe and the first die and a first surface of the encapsulant. A channel is cut through the encapsulant and leadframe to separate the contact pads. A plurality of conductive vias can be formed through the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive vias. | 11-17-2011 |
20110291249 | Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe - A semiconductor device has a prefabricated multi-die leadframe with a base and integrated raised die paddle and a plurality of bodies extending from the base. A thermal interface layer is formed over a back surface of a semiconductor die or top surface of the raised die paddle. The semiconductor die is mounted over the raised die paddle between the bodies of the leadframe with the TIM disposed between the die and raised die paddle. An encapsulant is deposited over the leadframe and semiconductor die. Vias can be formed in the encapsulant. An interconnect structure is formed over the leadframe, semiconductor die, and encapsulant, including into the vias. The base is removed to separate the bodies from the raised die paddle. The raised die paddle provides heat dissipation for the semiconductor die. The bodies are electrically connected to the interconnect structure. The bodies operate as conductive posts for electrical interconnect. | 12-01-2011 |
20120119388 | Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die - A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die. | 05-17-2012 |
20120153467 | Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die. | 06-21-2012 |
20120153505 | Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die. | 06-21-2012 |
20120168916 | Semiconductor Device and Method of Forming Open Cavity in TSV Interposer to Contain Semiconductor Die in WLCSMP - A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer. | 07-05-2012 |
20120292745 | Semiconductor Device and Method of Forming 3D Semiconductor Package with Semiconductor Die Stacked Over Semiconductor Wafer - A semiconductor device has a substrate and plurality of first semiconductor die having conductive vias formed through the first semiconductor die mounted with an active surface oriented toward the substrate. An interconnect structure, such as bumps or conductive pillars, is formed over the substrate between the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The second semiconductor die is electrically connected through the interconnect structure to the substrate and through the conductive vias to the first semiconductor die. An underfill material is deposited between the first semiconductor die and substrate. Discrete electronic components can be mounted to the substrate. A heat spreader or shielding layer is mounted over the first and second semiconductor die and substrate. Alternatively, an encapsulant is formed over the die and substrate and conductive vias or bumps are formed in the encapsulant electrically connected to the first die. | 11-22-2012 |
20130001762 | Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die - A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure. | 01-03-2013 |
20130087898 | Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die - A prefabricated multi-die leadframe having a plurality of contact pads is mounted over a temporary carrier. A first semiconductor die is mounted over the carrier between the contact pads of the leadframe. A second semiconductor die is mounted over the contact pads of the leadframe and over the first die. An encapsulant is deposited over the leadframe and first and second die. The carrier is removed. A first interconnect structure is formed over the leadframe and the first die and a first surface of the encapsulant. A channel is cut through the encapsulant and leadframe to separate the contact pads. A plurality of conductive vias can be formed through the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive vias. | 04-11-2013 |
20130099378 | Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die - A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die. | 04-25-2013 |
20130105970 | Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe | 05-02-2013 |
20130249104 | Semiconductor Device and Method of Forming Conductive Layer Over Metal Substrate for Electrical Interconnect of Semiconductor Die - A semiconductor device has a substrate with a cavity. A conductive layer is formed within the cavity and over the substrate outside the cavity. A plurality of indentations can be formed in a surface of the substrate opposite the cavity for stress relief. A first semiconductor die is mounted within the cavity. A plurality of conductive vias can be formed through the first semiconductor die. An insulating layer is disposed between the first semiconductor die and substrate with the first conductive layer embedded within the first insulating layer. An encapsulant is deposited over the first semiconductor die and substrate. An interconnect structure is formed over the encapsulant. The interconnect structure is electrically connected to the first semiconductor die and first conductive layer. The substrate is removed to expose the first conductive layer. A second semiconductor die is mounted to the conductive layer over the first semiconductor die. | 09-26-2013 |
20130299974 | Semiconductor Device and Method of Forming Open Cavity in TSV Interposer to Contain Semiconductor Die in WLCSMP - A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer. | 11-14-2013 |
20130299982 | Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die - A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die. | 11-14-2013 |
20140175639 | Semiconductor Device and Method of Simultaneous Molding and Thermalcompression Bonding - A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material. | 06-26-2014 |
20140175640 | Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer Form - A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate. | 06-26-2014 |
20140175661 | Semiconductor Device and Method of Making Bumpless Flipchip Interconnect Structures - A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate. | 06-26-2014 |
20140295618 | Methods of Manufacturing Flip Chip Semiconductor Packages Using Double-Sided Thermal Compression Bonding - Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package. | 10-02-2014 |
20140361423 | Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die - A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure. | 12-11-2014 |
20140367848 | Semiconductor Device and Method of Making an Embedded Wafer Level Ball Grid Array (EWLB) Package on Package (POP) Device With a Slotted Metal Carrier Interposer - A semiconductor device has a semiconductor die. The semiconductor die is disposed over a conductive substrate. An encapsulant is deposited over the semiconductor die. A first interconnect structure is formed over the encapsulant. An opening is formed through the substrate to isolate a portion of the substrate electrically connected to the first interconnect structure. A bump is formed over the first interconnect structure. Conductive vias are formed through the encapsulant and electrically connected to the portion of the substrate. A plurality of bumps is formed over the semiconductor die. A first conductive layer is formed over the encapsulant. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. Protrusions extend above the substrate. | 12-18-2014 |
Patent application number | Description | Published |
20100244223 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a shielding channel through a substrate first side and a substrate second side; mounting a first shielding interconnect to the shielding channel; mounting an integrated circuit over the substrate and adjacent to the first shielding interconnect; attaching a silicon interposer, having an integral-conductive-shield and a via, to the first shielding interconnect with the integral-conductive-shield over the integrated circuit; grounding the shielding channel at the substrate second side; and forming an encapsulation over the substrate covering the integrated circuit and the first shielding interconnect. | 09-30-2010 |
20100314736 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture an integrated circuit packaging system includes: providing a base substrate; mounting a first base integrated circuit over the base substrate; mounting a second base integrated circuit over the first base integrated circuit; attaching a stacking interconnect to the base substrate and adjacent to the first base integrated circuit; and forming a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect. | 12-16-2010 |
20100314738 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A STACK PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a stack board; connecting a device over the stack board; forming a stack encapsulant having a cavity and a pedestal over the device and having a shaped perimeter side from a pedestal surface of the pedestal to the stack board; and attaching a stack adhesive to a base package and the pedestal, the cavity and the shaped perimeter side providing a space for connections to the stack board. | 12-16-2010 |
20110024887 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA BASE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base having a through-conductor spanning the height of the base, and having an insulator protecting the base and the through-conductor; mounting a chip over the base and connected to the base with a first interconnect; forming a second interconnect above the base and horizontally beside the chip; and encapsulating the chip, the first interconnect, and the second interconnect with an encapsulation. | 02-03-2011 |
20110062574 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed. | 03-17-2011 |
20110068453 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATED VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; attaching a buffer interconnect to and over the substrate; forming an encapsulation over the substrate covering the buffer interconnect and the integrated circuit; and forming a via in the encapsulation and to the buffer interconnect. | 03-24-2011 |
20110068464 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a component over the base substrate; attaching a component interconnect to the base substrate and a perimeter of the component; mounting a stack device over the component; attaching a base exposed interconnect directly on the component and next to the component interconnect; and forming a base encapsulation over the base substrate, the component, and the component interconnect, the base exposed interconnect partially exposed from the base encapsulation. | 03-24-2011 |
20110140259 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate; coupling a conductive column lead frame to the base package substrate by: providing a lead frame support, patterning a conductive material on the lead frame support including forming an interconnect securing structure, and coupling the conductive material to the base package substrate; forming a base package body between the base package substrate and the conductive column lead frame; and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body. | 06-16-2011 |
20110204494 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a device over the component side; forming a shield connector on the component side adjacent the device; forming a package interconnect on the component side outside a region having the shield connector and the device; applying an encapsulant around the package interconnect, the shield connector, and the device; and mounting a shield structure on the encapsulant, the shield connector, and the device, with the package interconnect partially exposed. | 08-25-2011 |
20110215448 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a component side of the base package substrate, forming system contacts on a system side of the base package substrate, and forming a reference voltage circuit between the component contacts and the system contacts; mounting a first integrated circuit die on the component contacts; mounting a lead frame on the first integrated circuit die and coupled to the component contacts; and isolating a conductive shield from the lead frame, the conductive shield coupled to the reference voltage circuit. | 09-08-2011 |
20110215450 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a carrier having a cavity and a carrier top side adjacent to the cavity; mounting an integrated circuit in the cavity; forming an encapsulation surrounding the integrated circuit; and attaching a conductive channel to the carrier top side, the conductive channel over the encapsulation. | 09-08-2011 |
20110220395 | CARRIER SYSTEM WITH MULTI-TIER CONDUCTIVE POSTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a carrier system includes: providing a carrier base; forming a recess in the carrier base with the recess around a planar surface; forming a first barrier on the planar surface; forming a second barrier on the carrier base in the recess; forming a first post on the first barrier; and forming a second post on the second barrier. | 09-15-2011 |
20110223721 | METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS - A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a planar surface and a cavity therein, a first barrier between the planar surface and a first interconnect, and a second barrier between the cavity and a second interconnect; providing a substrate; mounting an integrated circuit over the substrate; mounting the carrier to the substrate with the first interconnect and the second interconnect attached to the substrate and with the planar surface over the integrated circuit; forming an encapsulation between the substrate and the carrier covering the integrated circuit, the encapsulation having an encapsulation recess under the planar surface and over the integrated circuit; and removing a portion of the carrier to expose the encapsulation, a portion of the first barrier to form a first contact pad, and a portion of the second barrier to form a second contact pad. | 09-15-2011 |
20110285009 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a first terminal; connecting an integrated circuit to the first terminal; forming a second terminal connected over the first terminal and the integrated circuit by a vertical conductive post integral with the first terminal or the second terminal; and encapsulating the integrated circuit and the vertical conductive post leaving portions of the first terminal and the second terminal exposed. | 11-24-2011 |
20110291283 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EMBEDDED DIE SUPERSTRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: providing a through-silicon-via die having conductive vias therethrough; forming a first redistribution layer on a bottom of the through-silicon-via die coupled to the conductive vias; forming a second redistribution layer on the top of the through-silicon-via die coupled to the conductive vias; fabricating an embedded die superstructure on the second redistribution layer including: mounting an integrated circuit die to the second redistribution layer, forming a core material layer on the second redistribution layer to be coplanar with the integrated circuit die, forming a first build-up layer, having contact links coupled to the integrated circuit die, on the core material layer, and coupling component interconnect pads to the contact links; and forming system interconnects on the first redistribution layer for coupling the through-silicon-via die, the integrated circuit die, the component interconnect pads, or a combination thereof. | 12-01-2011 |
20110298119 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: forming a non-inverted internal stacking module including: fabricating an internal stacking module (ISM) substrate having an ISM component side and an ISM coupling side, coupling an internal stacking module integrated circuit to the ISM component side, coupling stacking structures, adjacent to the internal stacking module integrated circuit, on the ISM component side, and molding a stacking module body having a top surface that is coplanar with and exposes the stacking structures; forming a base package substrate under the non-inverted internal stacking module; coupling middle structures between the base package substrate and the ISM coupling side; and forming a base package body on the base package substrate, the middle structures, and the non-inverted internal stacking module including exposing the top surface of the stacking module body to be coplanar with the base package body. | 12-08-2011 |
20110309492 | INTEGRATED CIRCUIT SYSTEM WITH RECESSED THROUGH SILICON VIA PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate with a face surface having a via therein and a back surface having a trench therein; filling the via with a conductive pillar; forming a recessed contact pad in the trench; filling the recessed contact pad partially with solder; and forming an under-bump metal having a base surface in electrical contact with the conductive pillar, and having sides that extend away from the face surface of the substrate and further extend beyond the base surface. | 12-22-2011 |
20120025398 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, and forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed. | 02-02-2012 |
20120068332 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a stack substrate with a component side; connecting an integrated circuit component to the component side; attaching a conductive post to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component; forming a protection layer on a top and sides of the protruded end, the protection layer having a width equal to a width of the conductive post; applying a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation; and mounting a base package under the stack substrate, base package connected to the stack substrate. | 03-22-2012 |
20120119393 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLEXIBLE SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a foldable segment, a base segment, and a stack segment; connecting a base substrate connector directly on the base segment; connecting a stack substrate connector directly on the stack segment; mounting a base integrated circuit over the base segment with the base substrate connector outside a perimeter of the base integrated circuit; and folding the package substrate with the stack segment over the base segment and the stack substrate connector directly on the base substrate connector. | 05-17-2012 |
20120228768 | INTEGRATED CIRCUIT PACKAGING SYSTEM USING B-STAGE POLYMER AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a bond pad; a B-stage polymer, having a dispersion of conductive particles therein, on the bond pad; and a bond ball inserted into the B-stage polymer for forming intermetallic structures between the bond ball and the bond pad. | 09-13-2012 |
20120241925 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacturing of an integrated circuit packaging system includes: providing a base substrate; mounting a first die over the base substrate; mounting a second die over the first die; attaching an interposer substrate over the first die with an attachment adhesive therebetween, the interposer substrate having a central cavity and the second die within the central cavity; attaching a lateral interconnect to a second active side away from the first die of the second die and to the interposer substrate; and encapsulating the first die and the second die. | 09-27-2012 |
20120306102 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base package carrier; mounting an interposer over the base package carrier; forming a base package encapsulation over the base package carrier and the interposer with the base package encapsulation having a cavity for exposing the interposer; and forming a support recess in the base package encapsulation between a non-horizontal edge of the base package encapsulation and the cavity. | 12-06-2012 |
20120319263 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTRA SUBSTRATE DIE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a through hole; mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side; connecting a first interconnect in direct contact with the integrated circuit and the substrate; applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive. | 12-20-2012 |
20120319294 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LASER HOLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; molding a first encapsulation above the substrate; forming a via through the first encapsulation; mounting an integrated circuit above the substrate and between sides of the first encapsulation; and forming a second encapsulation covering the integrated circuit and the first encapsulation. | 12-20-2012 |
20120319295 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a circuit structure having a circuit active side and a cavity from the circuit active side; mounting an integrated circuit device in the cavity; forming a base encapsulation, having a base first side facing away from the circuit active side, on the circuit active side, around the integrated circuit device, and in the cavity; forming a first conductive pin, having a first pin height, in the base encapsulation and traversing from the circuit active side to the base first side; forming a second conductive pin, having a second pin height equivalent to the first pin height, in the base encapsulation and traversing from the integrated circuit device to the base first side; and removing a portion of the circuit structure to form a circuit non-active side and expose the integrated circuit device and a base second side. | 12-20-2012 |
20120326324 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting an organic chip assembly on the base substrate, the organic chip assembly includes providing an assembly integrated circuit embedded in an organic cover, the organic cover having a through via, and the organic chip assembly having a vertical assembly side; forming a molded underfill encapsulating the vertical assembly side, and between the organic chip assembly and the base substrate; and removing a portion of the organic chip assembly and the molded underfill for forming a planarized assembly surface. | 12-27-2012 |
20130049208 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REDISTRIBUTION LAYER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral interconnect having a bond finger and a contact pad with a trace in direct contact with the bond finger and the contact pad, the bond finger vertically offset from the contact pad; connecting an integrated circuit die and the bond finger; and forming a module encapsulation on the integrated circuit die, the bond finger and the trace exposed from the module encapsulation. | 02-28-2013 |
20130056863 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STIFFENER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a stiffener, having a stiffener opening completely through the stiffener, on the substrate; molding an encapsulation on the substrate and directly on an outer upper periphery surface of the stiffener and exposing an inner upper periphery surface of the stiffener, the encapsulation exposing a portion of the substrate; mounting an integrated circuit over the substrate and within the perimeter of the stiffener; and attaching a lid plate on the inner upper periphery surface of the stiffener and over the integrated circuit, the lid plate extending above an encapsulation top side. | 03-07-2013 |
20130056864 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED THERMAL HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting a bottom integrated circuit on a bottom substrate having a peripheral thermal via connected to a peripheral thermal interconnect; mounting an inner heat shield, having a top planar portion, over the bottom integrated circuit with the inner heat shield connected to the peripheral thermal via; mounting a top integrated circuit over the inner heat shield; and forming a package encapsulation over the bottom integrated circuit, the inner heat shield, and the top integrated circuit with the top planar portion exposed only at each corners of a package topside of the package encapsulation. | 03-07-2013 |
20130075923 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation. | 03-28-2013 |
20130075927 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed. | 03-28-2013 |