Patent application number | Description | Published |
20090096007 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture. | 04-16-2009 |
20090130851 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, comprises forming a first film above a pattern forming material, patterning the first film to form a core material pattern, forming a second film above the pattern forming material so as to cover a side surface and an upper surface of the core material pattern, forming a third film above the second film as a protective material for the second film, etching the second and third films so that side wall sections including the second film and the third film are formed on both sides of the core material pattern and the second film and the third film of an area other than the side wall sections are removed, removing the core material pattern between the side wall sections, and transferring patterns corresponding to the side wall sections on the pattern forming material by using the side wall sections as a mask. | 05-21-2009 |
20090256178 | SEMICONDUCTOR DEVICE HAVING MISFETS AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a dielectric film and gate electrode that are stacked on a substrate, sidewalls formed to cover the side surfaces of the electrode and dielectric film, and SiGe films formed to sandwich the sidewalls, electrode and dielectric film, filled in portions separated from the sidewalls, having upper portions higher than the surface of the substrate and having silicide layers formed on regions of exposed from the substrate. The lower portion of the SiGe film that faces the electrode is formed to extend in a direction perpendicular to the surface of the substrate and the upper portion is inclined and separated farther apart from the gate electrode as the upper portion is separated away from the surface of the substrate. The surface of the silicide layer of the SiGe film that faces the gate electrode is higher than the channel region. | 10-15-2009 |
20100176368 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing semiconductor memory device comprises forming a first wiring layer and a memory cell layer above a semiconductor substrate; forming a plurality of first trenches extending in a first direction in the first wiring layer and the memory cell layer, thereby forming first wirings and separating the memory cell layer; burying a first interlayer film in the first trenches to form a stacked body; forming a second wiring layer above the stacked body; forming a plurality of second trenches, extending in a second direction intersecting the first direction and reaching an upper surface of the first interlayer film in depth, in the first stacked body with the second wiring layer formed thereabove, thereby forming second wirings; removing the first interlayer film isotropically; and digging the second trenches down to an upper surface of the first wirings, thereby forming memory cells. | 07-15-2010 |
20110097888 | Semiconductor memory device and method of manufacturing the same - A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture. | 04-28-2011 |
Patent application number | Description | Published |
20090212337 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate. | 08-27-2009 |
20090283819 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a substrate; a plurality of dielectric films and electrode films which are alternately stacked on the substrate and have a through hole penetrating in the stacking direction; a semiconductor pillar formed inside the through hole; and a charge storage layer provided at least between the semiconductor pillar and the electrode film. At least part of a side surface of a portion of the through hole located in the electrode film is sloped relative to the stacking direction. | 11-19-2009 |
20100323505 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a resist on a subject layer containing silicon. The method can etch the subject layer using the resist as a mask and with a gas containing a halogen element, which is introduced into a processing chamber. After the etching of the subject layer, the method can slim a planner size of the resist with oxygen gas and a gas containing a halogen element, which are introduced into the same processing chamber. | 12-23-2010 |
20110049607 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes: alternately stacking a plurality of insulating layers and electrode layers; forming a hole penetrating through a multilayer body of the insulating layers and the electrode layers; forming a conductive film on an inner wall of the hole; anisotropically etching the conductive film to selectively leave the conductive film on a sidewall of the hole; altering the conductive film into an insulator by heat treatment; and removing the insulator covering the electrode layers to expose the electrode layers into the hole. | 03-03-2011 |
20110079833 | Semiconductor device and method for manufacturing same - A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate. | 04-07-2011 |
Patent application number | Description | Published |
20110147942 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device of an embodiment includes: after forming a first interconnection layer and a memory cell layer above a semiconductor substrate, forming first lines by forming first grooves extending in first direction; forming a thin film on the side walls of the first grooves; forming a stack structure by filling an interlayer insulating film in the first grooves; forming a second interconnection layer above the stack structure; forming second lines by forming second grooves extending in second direction; removing the thin film exposed at bottom of the second grooves; and forming columnar memory cells by removing the memory cell layer exposed at bottom of the second grooves. The thin film has higher etching rate than the interlayer insulating film, and is removed prior to portions of the memory cell layer adjoining the thin film. | 06-23-2011 |
20120319173 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, THREE-DIMENSIONAL SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is. | 12-20-2012 |
20140284308 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS - There are provided a plasma etching method and a plasma etching apparatus, capable of suppressing occurrence of local bias in etching rate and suppressing occurrence of charge-up damage. The plasma etching method of etching a silicon layer of a substrate to be processed using the plasma etching apparatus sets the pressure in a processing chamber to 13.3 Pa or more and applies, to a lower electrode, a first high-frequency power with a first frequency and a second high-frequency power with a second frequency that is lower than the first frequency and is a frequency of 1 MHz or lower. | 09-25-2014 |
Patent application number | Description | Published |
20110183497 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include multiply stacking an insulating layer and a conductive layer alternately above a base member. The insulating layer includes silicon oxide. The conductive layer includes silicon. In addition, the method can form a SiOC film on a stacked body of the insulating layers and the conductive layers, pattern the SiOC film, and make a hole in the stacked body by etching the insulating layers and the conductive layers using the patterned SiOC film as a mask. | 07-28-2011 |
20110201167 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a stacked body by alternately stacking a plurality of insulating layers and a plurality of conductive layers above a substrate and forming a resist film above the stacked body. The method can include plasma-etching the insulating layers and the conductive layers by using the resist film as a mask. The method can include forming a hardened layer in an upper surface of the resist film by plasma treatment using a gas containing at least one selected from a group consisting of boron, phosphorus, arsenic, antimony, silicon, germanium, aluminum, gallium, and indium. The method can include slimming a plane size of the resist film by plasma treatment using an oxygen-containing gas in a state where the hardened layer is formed in the upper surface of the resist film. | 08-18-2011 |
20110223769 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - According to one embodiment, a method of fabricating a semiconductor device, including, selectively forming a first film as a core member on a film to be processed, forming a second film on a side surface and an upper surface of the core member, and on an upper surface of the film to be processed to cover the film, the second film which is constituted with same material as the first film and is doped with impurities being different in amount from impurities in the first film, removing the second film on the core member and on the film to be processed to form a sidewall mask constituted with the second film on the side surface of the core member, selectively removing the core member, and etching the film to be processed using the sidewall mask film as a mask. | 09-15-2011 |
20110291178 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a lower gate layer, a stacked body, a dummy electrode layer, an insulating film, and a channel body. The lower gate layer is provided above the substrate. The stacked body includes a plurality of insulating layers and a plurality of electrode layers alternately stacked above the lower gate layer. The dummy electrode layer is provided between the lower gate layer and the stacked body, made of the same material as the electrode layer, and thicker than each of the electrode layers. The insulating film includes a charge storage film provided on a side wall of a hole formed to penetrate through the stacked body and the dummy electrode layer. The channel body is provided on an inside of the insulating film in the hole. | 12-01-2011 |
20120018796 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structures, first and second semiconductor pillars, first and second memory units, and a semiconductor connection portion. The stacked structures include electrode films and first inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is aligned with the first stacked structure in a second direction perpendicular to the first. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The first and second memory units are provided between the electrode films and the semiconductor pillar, respectively. The semiconductor connection portion connects the first and second semiconductor pillars and includes: an end connection portion; and a first protrusion having a side face continuous with a side face of the first semiconductor pillar. The semiconductor connection portion does not include a portion smaller than a diameter of the first semiconductor pillar. | 01-26-2012 |
20120211816 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor memory device includes: forming a stacked body including insulating films stacked alternately with electrode films, a memory hole is made in one portion of the stacked body to extend in a stacking direction, a charge storage layer is provided on an inner surface of the memory hole, a semiconductor member is provided in the memory hole; forming a hard mask on the stacked body, the hard mask has a plurality of holes of mutually different sizes; | 08-23-2012 |
20130234232 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes forming a part of a stacked body including a plurality of conductive films and a plurality of first insulating films alternately stacked into a shape of steps to form a plurality of stepped portions of different heights, each stepped portion having the first insulating film as a top face. The method includes forming gaps under ends of the first insulating films by removing ends of the conductive films under the first insulating films in the stepped portions. The method includes forming second insulating films on the respective stepped portions and in the gaps. The method includes forming a plurality of vias, each of the vias penetrating through the second insulating film and the first insulating film in each stepped portion and reaches the conductive film in each stepped portion. | 09-12-2013 |
20130234235 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a manufacturing method of a semiconductor memory device is disclosed. The method can include forming a stacked body on a substrate. The stacked body includes first silicon films containing impurities and having a concentration difference of the impurities provided among different layers, and non-doped second silicon films each provided between the first silicon films. The method can include forming a hole in the stacked body. The method can include removing the second silicon films by etching through the hole and forming an inter-electrode space between the first silicon films. The method can include forming a memory film including a charge storage film on a side wall of the hole and also forming at least a part of the memory film in the inter-electrode space. | 09-12-2013 |