Patent application number | Description | Published |
20100061490 | Timing Phase Detection Using a Matched Filter Set - Various embodiments of the present invention provide systems and methods for phase identification in data processing systems. As one example, a circuit is disclosed that includes a bank of matched filters with two or more matched filters tuned to detect patterns corresponding to a timing pattern sampled using different phases of a sample clock. In particular, the bank of matched filters includes at least a first matched filter tuned to detect a first pattern corresponding to the timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock. The circuits further include a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter. | 03-11-2010 |
20100061492 | Reduced Frequency Data Processing Using a Matched Filter Set Front End - Various embodiments of the present invention provide systems and methods for reduced clock rate data processing. As an example, a circuit is disclosed that includes a matched filter bank that receives a series of symbols at a rate corresponding to a sample clock. The matched filter bank includes a first matched filter tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and a second matched filter tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence. The circuit further includes a detector circuit that processes a series of symbol proxies including the first symbol proxy and the second symbol proxy at a rate corresponding to a reduced rate clock. The reduced rate clock is the sample clock divided by a factor. | 03-11-2010 |
20100067621 | Feed Forward Detector for Pattern Dependent Noise Prediction - Various embodiments of the present invention provide systems and methods for processing data. As one example, a circuit is disclosed that includes a digital input signal that is provided to a pre-detector that detects an estimated pattern in the digital input signal. In addition, the digital input signal is provided to a summation element that subtracts the estimated pattern from the digital input signal to yield a noise estimate. The noise estimate is provided to a data dependent noise prediction filter that is statically tuned to detect a highly correlated noise pattern, and provides a filtered noise estimate. In some cases, the circuit further includes a post-detector that performs a data detection process on the digital input signal reduced by the filtered noise estimate. | 03-18-2010 |
20100067628 | Adaptive Pattern Dependent Noise Prediction on a Feed Forward Noise Estimate - Various embodiments of the present invention provide systems and methods for processing data. As one example, a circuit is disclosed that includes a pre-detector that detects an estimated pattern in a digital input signal, and a summation element that subtracts the estimated pattern from the digital input signal to yield a noise estimate. The circuit further includes a data dependent noise prediction filter that is adaptively tuned to detect a noise pattern, and that filters the noise estimate to provide a filtered noise estimate. | 03-18-2010 |
20100156525 | Method and System for Tuning Precision Continuous-Time Filters - Described embodiments provide a method for calibrating a continuous-time filter having at least one adjustable parameter. A square-wave signal is filtered by a continuous-time filter having a cutoff frequency less than fs. The filtered signal is quantized at the rate fs. An N-point Fourier transform is performed of the quantized signal into N real output values and N imaginary output values. At least one of the real output values are accumulated to form a real output signal and at least one of the imaginary output values are accumulated to form an imaginary output signal. The real and imaginary output signals are summed to form an output signal, which is then squared. The squared output signal is compared to a comparison value. At least one parameter of the continuous-time filter is adjusted based upon the comparison. The steps are repeated until the squared output signal is approximately the comparison value. | 06-24-2010 |
20100161700 | Apparatus for Calculating an N-Point Discrete Fourier Transform - Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count. | 06-24-2010 |
20130159368 | Method and Apparatus for Calculating an N-Point Discrete Fourier Transform - Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count. | 06-20-2013 |
Patent application number | Description | Published |
20110131351 | Coalescing Multiple Contexts into a Single Data Transfer in a Media Controller Architecture - Described embodiments provide for transferring data between a host device and a storage media. A host data transfer request is received and a total size of the data transfer is determined. One or more contexts corresponding to the total size of the requested transfer are generated and are associated with transfers of data. If the data transfer is a write operation, one or more data segments from the host device are transferred into a buffer. The combined size of the data segments corresponds to the total size of the data transfer. In accordance with the contexts, the one or more data segments are transferred from the buffer to the storage media. If the requested data transfer is a read operation, in accordance with the contexts, data from the storage media is retrieved into a buffer and grouped into one or more segments, which are transmitted to the host device. | 06-02-2011 |
20110131357 | Interrupt Queuing in a Media Controller Architecture - Described embodiments provide a media controller for servicing contexts corresponding to data transfer requests from host devices. The media controller includes a context generator for generating contexts corresponding to the data transfer requests and a buffer for storing one or more context pointers, each pointer corresponding to a context and an action by a system module associated with the context. A context processor is configured to complete a context when the action by a media controller module associated with the context is complete, remove each pointer from the buffer associated with the completed context, and determine whether an interrupt corresponds to the completed context and removed pointer. If no interrupt corresponds to the completed context, the completed context is cleared. If an interrupt corresponds to the completed context, the interrupt is provided to a master processor and a completed context recycler for recycling the completed context pointer to the context generator. | 06-02-2011 |
20110131360 | Context Execution in a Media Controller Architecture - Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media. | 06-02-2011 |
20110131374 | Direct Memory Access for Loopback Transfers in a Media Controller Architecture - Described embodiments provide for transferring data from one location to another location in a memory of a media controller. A transmit data path and a receive data path of the media controller are linked with a generic direct memory access (GDMA). The transmit data path includes a transmit (TX) buffer and the receive data path includes a receive (RX) buffer. The GDMA is programmed with a total transfer count and a transfer mode. The GDMA processes the movable data based on the total transfer count and the transfer mode by converting one or more portions of the movable data in the TX buffer into a predefined frame structure defined with status entries, which translates frames of the moveable data between the TX data path and the RX data path and synchronizes the movable data between the TX buffer and the RX buffer with the status entries. | 06-02-2011 |
20110131375 | Command Tag Checking in a Multi-Initiator Media Controller Architecture - Described embodiments provide a method of allocating resources of a media controller for a data transfer. A data transfer request is received from at least one host device, and includes a host device ID and a data transfer request ID. The media controller generates a Tag ID of the data transfer request based on the host device ID and the data transfer request ID, and generates a starting memory address of a tag table based on the Tag ID of the data transfer request. A tag count value is read from the starting memory address of the tag table. If the tag count value reaches a threshold, an absence of a tag overlap is determined and the Tag ID of the data transfer request is added to the tag table at the starting memory address. | 06-02-2011 |