Patent application number | Description | Published |
20090322379 | PEAK HOLD CIRCUIT - A peak hold circuit includes an input transistor, which is provided with an input signal, and a first hold capacitor, which holds a maximum or minimum value of the input signal. A correction circuit, which corrects the hold voltage held by the first hold capacitor, includes an operational amplifier, which is supplied with the hold voltage, and a correction transistor, which is provided with an output signal of the operational amplifier. A source/emitter of the correction transistor is coupled to the operational amplifier. The peak hold circuit also includes a current detection circuit, which detects current flowing to the input transistor, and a peak current hold circuit, which holds the peak value of the current detected by the current detection circuit as a peak current and supplies the peak current to the correction transistor. | 12-31-2009 |
20100007427 | SWITCHING CAPACITOR GENERATION CIRCUIT - A switching capacitor generation circuit which reduces the on-resistance and parasitic capacitance of a switch element and improves the operation properties of the switch element. The switching capacitor generation circuit, which has first and second output terminals, includes a first capacitor coupled to the first output terminal, a second capacitor coupled to the second output terminal, and a single switch element coupled between the first and the second capacitors. | 01-14-2010 |
20100013567 | SWITCHING CAPACITOR GENERATION CIRCUIT - A switching capacitor generation circuit which reduces the on-resistance and parasitic capacitance of a switch element and improves the operation properties of the switch element. The switching capacitor generation circuit, which has first and second output terminals, includes a first capacitor coupled to the first output terminal, a second capacitor coupled to the second output terminal, and a single switch element coupled between the first and the second capacitors. | 01-21-2010 |
20100330933 | OUTPUT CIRCUIT OF HIGH-FREQUENCY TRANSMITTER - A transmitting and receiving device includes: a transmission circuit that transmits a signal by FM-modulating a carrier wave of the signal; an FM demodulation circuit that generates a demodulation signal by FM-demodulating the received signal; and a first filter circuit that changes a pass-band for letting the received signal pass through according to the demodulation signal, wherein the transmitting and receiving device perform a power supply line communication through the power supply line in which a signal is transmitted and received among a plurality of the transmitting and receiving devices. | 12-30-2010 |
Patent application number | Description | Published |
20080201598 | Device and Method For Preventing Lost Synchronization - A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses. | 08-21-2008 |
20080310570 | DEVICE AND METHOD FOR PREVENTING LOST SYNCHRONIZATION - A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses. | 12-18-2008 |
20090129303 | DATA TRANSMISSION CIRCUIT AND ITS CONTROL METHOD - A data transmission circuit transmitting an activation signal prior to a data signal through a signal transmission line, including: an activation detection signal generation unit for generating an activation detection signal by detecting the activation signal; and a wakeup signal generation unit for being activated by the activation detection signal, and generating a wakeup signal by detecting that the activation signal is transmitted for a predetermined time. | 05-21-2009 |
20110216863 | RECEIVING APPARATUS AND METHOD FOR SETTING GAIN - A receiving apparatus includes: a clock-data recovery circuit to generate a clock based on receive data and a setting circuit to set a gain of a filtering process to filter a phase difference between the receive data and the clock. | 09-08-2011 |
20130243139 | DEVICE AND METHOD FOR PREVENTING LOST SYNCHRONIZATION - A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method includes performing a synchronization process to establish synchronization between the connection nodes based on the synchronization clock, performing a connection failure process when the synchronization is not established when a first time elapses after receiving the input data, correcting the clock data recovery circuit when the synchronization is not established when a second time elapses after receiving the input data, wherein the second time is shorter than the first time, and performing a resynchronization process to establish synchronization between the connection nodes based on a synchronization clock, which is generated by the clock data recovery circuit that has been corrected, before the first time elapses and after the second time elapses. | 09-19-2013 |
20130287154 | DEVICE AND METHOD FOR PREVENTING LOST SYNCHRONIZATION - A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses. | 10-31-2013 |